Re: [Xen-users] The saga of Heterodyne's PCI Passthrough

["Drake Wilson" <drake@xxxxxxxxxxxxxx>]

[...]

Hmm.  Loopiness follows.

So I finally chased down somewhere on the Web saying that MSI delivery modes
are similar to IPI delivery modes, and then I found the IPI types in the AMD64
architecture manual.  Apparently mode 3 is a remote read from a separate local
APIC.  This sounds totally bogus for an interrupt coming from a graphics card,
but I don't know for sure.

But after poring over the dmesg a bit more I realized a bunch of lower
interrupts were being eaten by PnP devices.  I suppose these are attached to
things like the emulated PS/2 keyboard.  Since I don't need those (I use the
serial device as emergency maintenance port), pnpacpi=off pnpbios=off in the
domU kernel, and magically there's enough interrupts to pass through both the
Radeon and the USB controller, or so it seems.

So that may be a good enough workaround for now.  But I still want to know why
those MSIs are apparently not being passed through.

Also apparently the interrupt limit is an architectural one, which I should
have known since it was hardcoded, but somewhere in there I made a logic error
I suppose (keeping in mind that I really don't know what I'm doing here).

Some primitive attempts to trace back where in the world mode 3 is coming from
yielded not much except for a twisty maze that points either into the guest OS
or maybe into some sort of structure corruption in the device model, maybe;
the only places that I could find where a Linux write_msi happens that would
alter the MSI Message Data register that way (as opposed to setting it to
hardcoded elements) are related to IOMMU stuff, such as io_apic.c:3051, and
some further primitive attempts to probe this yielded nothing useful.

I do notice that Linux xen_hvm_setup_msi_irqs doesn't seem to get called
anywhere, or at least its printk lines don't show up in dmesg, but whether
this is relevant I cannot say.

Kyaieee!

   ---> Drake Wilson

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