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xen-users
RE: [Xen-users] Re: [Xen-devel] VMX Hardware
I hope you aren't in a hurry to do your benchmarking on AMD's Nested
Page Tables since their initial launch of Pacifica won't include this
support.
This info came from an AMD "fellow" (sorry--names have eluded
me--"Richard Brunner" seems right) at the Xen BoF @ Linux World (8/10)
who indicated that this functionality will be added in later. This was
the same BoF where Intel demonstrated Win XP running natively on Xen on
a development VT platform -- good stuff.
Disclaimer: Intel also noted at the same meeting that their ultimate for
roadmap for VT (the new name for Vanderpool) will also be delivered in
staged releases.
Shane O.
-----Original Message-----
From: xen-users-bounces@xxxxxxxxxxxxxxxxxxx
[mailto:xen-users-bounces@xxxxxxxxxxxxxxxxxxx] On Behalf Of Keir Fraser
Sent: Sunday, August 14, 2005 2:23 PM
To: Anthony Liguori
Cc: Goetz Bock; xen-devel@xxxxxxxxxxxxxxxxxxx;
xen-users@xxxxxxxxxxxxxxxxxxx; monz@xxxxxxxxx
Subject: Re: [Xen-users] Re: [Xen-devel] VMX Hardware
On 14 Aug 2005, at 19:09, Anthony Liguori wrote:
> The Pacifica spec does mention optional hardware support for "Nested
> Page Tables" which is essentially hardware shadow page tables.
>
> Should be interesting to see the performance difference between
> software/hardware shadow page tables.
I have doubts about the performance of hardware page tables, unless
there's a clever TLB design. A pagetable walk which is four memory
accesses on normal x86/64 becomes twenty accesses in nested mode!
It may be that shadow pagetables, by providing a bigger 'cache' for
guest->host mappings, can actually perform better on many workloads.
I guess we'll see -- if silicon is produced that supports that mode,
someone is bound to add support to Xen.
-- Keir
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