# HG changeset patch
# User Jimi Xenidis <jimix@xxxxxxxxxxxxxx>
# Node ID 0a541b530f6a91b0a4de25db25c0ed33f0779202
# Parent c16586000525f9d9dfbbe336d9d458dd08b44a0e
[XEN][POWERPC] big lock to protect some TLB operations
970 requires locking around TLB operations, see code comment.
Signed-off-by: Jimi Xenidis <jimix@xxxxxxxxxxxxxx>
---
xen/arch/powerpc/papr/xlate.c | 17 ++++++++++++++++-
1 files changed, 16 insertions(+), 1 deletion(-)
diff -r c16586000525 -r 0a541b530f6a xen/arch/powerpc/papr/xlate.c
--- a/xen/arch/powerpc/papr/xlate.c Wed Jan 17 19:37:20 2007 -0500
+++ b/xen/arch/powerpc/papr/xlate.c Sat Jan 20 18:57:15 2007 -0500
@@ -72,6 +72,20 @@ static inline void pte_insert(union pte
}
#endif
+/*
+ * POWER Arch 2.03 Sec 4.12.1 (Yes 970 is one)
+ *
+ * when a tlbsync instruction has been executed by a processor in a
+ * given partition, a ptesync instruction must be executed by that
+ * processor before a tlbie or tlbsync instruction is executed by
+ * another processor in that partition.
+ *
+ * So for now, here is a BFLock to deal with it, the lock should be per-domain.
+ *
+ * XXX Will need to audit all tlb usege soon enough.
+ */
+
+static DEFINE_SPINLOCK(native_tlbie_lock);
static void pte_tlbie(union pte volatile *pte, ulong ptex)
{
ulong va;
@@ -91,6 +105,7 @@ static void pte_tlbie(union pte volatile
va = (pi << 12) | (vsid << 28);
va &= ~(0xffffULL << 48);
+ spin_lock(&native_tlbie_lock);
#ifndef FLUSH_THE_WHOLE_THING
if (pte->bits.l) {
va |= (pte->bits.rpn & 1);
@@ -114,7 +129,7 @@ static void pte_tlbie(union pte volatile
}
}
#endif
-
+ spin_unlock(&native_tlbie_lock);
}
long pte_enter(ulong flags, ulong ptex, ulong vsid, ulong rpn)
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