# HG changeset patch
# User Jimi Xenidis <jimix@xxxxxxxxxxxxxx>
# Node ID 7b25f1309eb19dc548fc5c1359b584b7eda23887
# Parent 32b10ed507f1f4c8ce4f0e10c9f8a2e4e124e2ae
[ppc] Turn on Save and Restore of VMX registers
Signed-off-by: Jimi Xenidis <jimix@xxxxxxxxxxxxxx>
---
xen/arch/ppc/float.S | 141 ++++++++++++++++++-------------------
xen/arch/ppc/ppc64/asm-offsets.c | 3
xen/include/asm-ppc/domain.h | 8 +-
xen/include/asm-ppc/ppc64/config.h | 1
4 files changed, 83 insertions(+), 70 deletions(-)
diff -r 32b10ed507f1 -r 7b25f1309eb1 xen/arch/ppc/float.S
--- a/xen/arch/ppc/float.S Tue Jun 13 15:00:54 2006 -0400
+++ b/xen/arch/ppc/float.S Tue Jun 13 15:14:57 2006 -0400
@@ -102,6 +102,9 @@ load_fp:
#endif /* HAS_FLOAT */
#ifdef HAS_VMX
+
+#define VCPU_vr(n) (VCPU_vrs + ((n) * 16))
+
/* So you might think that we could use the VRSAVE register to
* streamline this but "If this [VRSAVE] approach is taken it must be
* applied rigorously".
@@ -111,18 +114,18 @@ load_fp:
*/
save_vmx:
mfspr r0,SPRN_VRSAVE
- stw r0,CT_VRSAVE(r3)
+ stw r0,VCPU_vrsave(r3)
/* r0 as the second operand is considered 0 */
- addi r0,r3,CT_VR0 ; stvxl vr0,r0,r0
- addi r0,r3,CT_VR1 ; stvxl vr1,r0,r0
- addi r0,r3,CT_VR2 ; stvxl vr2,r0,r0
- addi r0,r3,CT_VR3 ; stvxl vr3,r0,r0
- addi r0,r3,CT_VR4 ; stvxl vr4,r0,r0
- addi r0,r3,CT_VR5 ; stvxl vr5,r0,r0
- addi r0,r3,CT_VR6 ; stvxl vr6,r0,r0
- addi r0,r3,CT_VR7 ; stvxl vr7,r0,r0
- addi r0,r3,CT_VR8 ; stvxl vr8,r0,r0
+ addi r0,r3,VCPU_vr(0); stvxl vr0,r0,r0
+ addi r0,r3,VCPU_vr(1); stvxl vr1,r0,r0
+ addi r0,r3,VCPU_vr(2); stvxl vr2,r0,r0
+ addi r0,r3,VCPU_vr(3); stvxl vr3,r0,r0
+ addi r0,r3,VCPU_vr(4); stvxl vr4,r0,r0
+ addi r0,r3,VCPU_vr(5); stvxl vr5,r0,r0
+ addi r0,r3,VCPU_vr(6); stvxl vr6,r0,r0
+ addi r0,r3,VCPU_vr(7); stvxl vr7,r0,r0
+ addi r0,r3,VCPU_vr(8); stvxl vr8,r0,r0
/*
* By now vr0 should be pushed out so now is a good time to
@@ -130,77 +133,77 @@ save_vmx:
* on the following operations.
*/
mfvscr vr0
- addi r0,r3,CT_VSCR ; stvxl vr0,r0,r0
-
- addi r0,r3,CT_VR9 ; stvxl vr9,r0,r0
- addi r0,r3,CT_VR10 ; stvxl vr10,r0,r0
- addi r0,r3,CT_VR11 ; stvxl vr11,r0,r0
- addi r0,r3,CT_VR12 ; stvxl vr12,r0,r0
- addi r0,r3,CT_VR13 ; stvxl vr13,r0,r0
- addi r0,r3,CT_VR14 ; stvxl vr14,r0,r0
- addi r0,r3,CT_VR15 ; stvxl vr15,r0,r0
- addi r0,r3,CT_VR16 ; stvxl vr16,r0,r0
- addi r0,r3,CT_VR17 ; stvxl vr17,r0,r0
- addi r0,r3,CT_VR18 ; stvxl vr18,r0,r0
- addi r0,r3,CT_VR19 ; stvxl vr19,r0,r0
- addi r0,r3,CT_VR20 ; stvxl vr20,r0,r0
- addi r0,r3,CT_VR21 ; stvxl vr21,r0,r0
- addi r0,r3,CT_VR22 ; stvxl vr22,r0,r0
- addi r0,r3,CT_VR23 ; stvxl vr23,r0,r0
- addi r0,r3,CT_VR24 ; stvxl vr24,r0,r0
- addi r0,r3,CT_VR25 ; stvxl vr25,r0,r0
- addi r0,r3,CT_VR26 ; stvxl vr26,r0,r0
- addi r0,r3,CT_VR27 ; stvxl vr27,r0,r0
- addi r0,r3,CT_VR28 ; stvxl vr28,r0,r0
- addi r0,r3,CT_VR29 ; stvxl vr29,r0,r0
- addi r0,r3,CT_VR30 ; stvxl vr30,r0,r0
- addi r0,r3,CT_VR31 ; stvxl vr31,r0,r0
+ addi r0,r3,VCPU_vscr ; stvxl vr0,r0,r0
+
+ addi r0,r3,VCPU_vr(9); stvxl vr9,r0,r0
+ addi r0,r3,VCPU_vr(10); stvxl vr10,r0,r0
+ addi r0,r3,VCPU_vr(11); stvxl vr11,r0,r0
+ addi r0,r3,VCPU_vr(12); stvxl vr12,r0,r0
+ addi r0,r3,VCPU_vr(13); stvxl vr13,r0,r0
+ addi r0,r3,VCPU_vr(14); stvxl vr14,r0,r0
+ addi r0,r3,VCPU_vr(15); stvxl vr15,r0,r0
+ addi r0,r3,VCPU_vr(16); stvxl vr16,r0,r0
+ addi r0,r3,VCPU_vr(17); stvxl vr17,r0,r0
+ addi r0,r3,VCPU_vr(18); stvxl vr18,r0,r0
+ addi r0,r3,VCPU_vr(19); stvxl vr19,r0,r0
+ addi r0,r3,VCPU_vr(20); stvxl vr20,r0,r0
+ addi r0,r3,VCPU_vr(21); stvxl vr21,r0,r0
+ addi r0,r3,VCPU_vr(22); stvxl vr22,r0,r0
+ addi r0,r3,VCPU_vr(23); stvxl vr23,r0,r0
+ addi r0,r3,VCPU_vr(24); stvxl vr24,r0,r0
+ addi r0,r3,VCPU_vr(25); stvxl vr25,r0,r0
+ addi r0,r3,VCPU_vr(26); stvxl vr26,r0,r0
+ addi r0,r3,VCPU_vr(27); stvxl vr27,r0,r0
+ addi r0,r3,VCPU_vr(28); stvxl vr28,r0,r0
+ addi r0,r3,VCPU_vr(29); stvxl vr29,r0,r0
+ addi r0,r3,VCPU_vr(30); stvxl vr30,r0,r0
+ addi r0,r3,VCPU_vr(31); stvxl vr31,r0,r0
blr
load_vmx:
- lwz r0,CT_VRSAVE(r3)
+ lwz r0,VCPU_vrsave(r3)
mtspr SPRN_VRSAVE,r0
/*
* This operation can take a long time so we use vr31 to
* eliminate the depency on r0 for the next load
*/
- addi r0,r3,CT_VSCR ; lvxl vr31,r0,r0
+ addi r0,r3,VCPU_vscr ; lvxl vr31,r0,r0
mtvscr vr31
/* r0 as the second operand is considered 0 */
- addi r0,r3,CT_VR0 ; lvxl vr0,r0,r0
- addi r0,r3,CT_VR1 ; lvxl vr1,r0,r0
- addi r0,r3,CT_VR2 ; lvxl vr2,r0,r0
- addi r0,r3,CT_VR3 ; lvxl vr3,r0,r0
- addi r0,r3,CT_VR4 ; lvxl vr4,r0,r0
- addi r0,r3,CT_VR5 ; lvxl vr5,r0,r0
- addi r0,r3,CT_VR6 ; lvxl vr6,r0,r0
- addi r0,r3,CT_VR7 ; lvxl vr7,r0,r0
- addi r0,r3,CT_VR8 ; lvxl vr8,r0,r0
- addi r0,r3,CT_VR9 ; lvxl vr9,r0,r0
- addi r0,r3,CT_VR10 ; lvxl vr10,r0,r0
- addi r0,r3,CT_VR11 ; lvxl vr11,r0,r0
- addi r0,r3,CT_VR12 ; lvxl vr12,r0,r0
- addi r0,r3,CT_VR13 ; lvxl vr13,r0,r0
- addi r0,r3,CT_VR14 ; lvxl vr14,r0,r0
- addi r0,r3,CT_VR15 ; lvxl vr15,r0,r0
- addi r0,r3,CT_VR16 ; lvxl vr16,r0,r0
- addi r0,r3,CT_VR17 ; lvxl vr17,r0,r0
- addi r0,r3,CT_VR18 ; lvxl vr18,r0,r0
- addi r0,r3,CT_VR19 ; lvxl vr19,r0,r0
- addi r0,r3,CT_VR20 ; lvxl vr20,r0,r0
- addi r0,r3,CT_VR21 ; lvxl vr21,r0,r0
- addi r0,r3,CT_VR22 ; lvxl vr22,r0,r0
- addi r0,r3,CT_VR23 ; lvxl vr23,r0,r0
- addi r0,r3,CT_VR24 ; lvxl vr24,r0,r0
- addi r0,r3,CT_VR25 ; lvxl vr25,r0,r0
- addi r0,r3,CT_VR26 ; lvxl vr26,r0,r0
- addi r0,r3,CT_VR27 ; lvxl vr27,r0,r0
- addi r0,r3,CT_VR28 ; lvxl vr28,r0,r0
- addi r0,r3,CT_VR29 ; lvxl vr29,r0,r0
- addi r0,r3,CT_VR30 ; lvxl vr30,r0,r0
- addi r0,r3,CT_VR31 ; lvxl vr31,r0,r0
+ addi r0,r3,VCPU_vr(0); lvxl vr0,r0,r0
+ addi r0,r3,VCPU_vr(1); lvxl vr1,r0,r0
+ addi r0,r3,VCPU_vr(2); lvxl vr2,r0,r0
+ addi r0,r3,VCPU_vr(3); lvxl vr3,r0,r0
+ addi r0,r3,VCPU_vr(4); lvxl vr4,r0,r0
+ addi r0,r3,VCPU_vr(5); lvxl vr5,r0,r0
+ addi r0,r3,VCPU_vr(6); lvxl vr6,r0,r0
+ addi r0,r3,VCPU_vr(7); lvxl vr7,r0,r0
+ addi r0,r3,VCPU_vr(8); lvxl vr8,r0,r0
+ addi r0,r3,VCPU_vr(9); lvxl vr9,r0,r0
+ addi r0,r3,VCPU_vr(10); lvxl vr10,r0,r0
+ addi r0,r3,VCPU_vr(11); lvxl vr11,r0,r0
+ addi r0,r3,VCPU_vr(12); lvxl vr12,r0,r0
+ addi r0,r3,VCPU_vr(13); lvxl vr13,r0,r0
+ addi r0,r3,VCPU_vr(14); lvxl vr14,r0,r0
+ addi r0,r3,VCPU_vr(15); lvxl vr15,r0,r0
+ addi r0,r3,VCPU_vr(16); lvxl vr16,r0,r0
+ addi r0,r3,VCPU_vr(17); lvxl vr17,r0,r0
+ addi r0,r3,VCPU_vr(18); lvxl vr18,r0,r0
+ addi r0,r3,VCPU_vr(19); lvxl vr19,r0,r0
+ addi r0,r3,VCPU_vr(20); lvxl vr20,r0,r0
+ addi r0,r3,VCPU_vr(21); lvxl vr21,r0,r0
+ addi r0,r3,VCPU_vr(22); lvxl vr22,r0,r0
+ addi r0,r3,VCPU_vr(23); lvxl vr23,r0,r0
+ addi r0,r3,VCPU_vr(24); lvxl vr24,r0,r0
+ addi r0,r3,VCPU_vr(25); lvxl vr25,r0,r0
+ addi r0,r3,VCPU_vr(26); lvxl vr26,r0,r0
+ addi r0,r3,VCPU_vr(27); lvxl vr27,r0,r0
+ addi r0,r3,VCPU_vr(28); lvxl vr28,r0,r0
+ addi r0,r3,VCPU_vr(29); lvxl vr29,r0,r0
+ addi r0,r3,VCPU_vr(30); lvxl vr30,r0,r0
+ addi r0,r3,VCPU_vr(31); lvxl vr31,r0,r0
blr
#endif /* HAS_VMX */
diff -r 32b10ed507f1 -r 7b25f1309eb1 xen/arch/ppc/ppc64/asm-offsets.c
--- a/xen/arch/ppc/ppc64/asm-offsets.c Tue Jun 13 15:00:54 2006 -0400
+++ b/xen/arch/ppc/ppc64/asm-offsets.c Tue Jun 13 15:14:57 2006 -0400
@@ -52,6 +52,9 @@ void __dummy__(void)
OFFSET(VCPU_fprs, struct vcpu, arch.fprs);
OFFSET(VCPU_fpscr, struct vcpu, arch.ctxt.fpscr);
+ OFFSET(VCPU_vrs, struct vcpu, arch.vrs);
+ OFFSET(VCPU_vscr, struct vcpu, arch.vscr);
+ OFFSET(VCPU_vrsave, struct vcpu, arch.vrsave);
OFFSET(VCPU_dec, struct vcpu, arch.dec);
OFFSET(VCPU_processor, struct vcpu, processor);
diff -r 32b10ed507f1 -r 7b25f1309eb1 xen/include/asm-ppc/domain.h
--- a/xen/include/asm-ppc/domain.h Tue Jun 13 15:00:54 2006 -0400
+++ b/xen/include/asm-ppc/domain.h Tue Jun 13 15:14:57 2006 -0400
@@ -53,6 +53,10 @@ struct slb_entry {
struct xencomm;
+typedef struct {
+ u32 u[4];
+} __attribute__((aligned(16))) vector128;
+
struct arch_vcpu {
cpu_user_regs_t ctxt; /* User-level CPU registers */
@@ -60,7 +64,9 @@ struct arch_vcpu {
double fprs[NUM_FPRS];
#endif
#ifdef HAS_VMX
- /* XXX VMX regs */
+ vector128 vrs[32];
+ vector128 vscr;
+ u32 vrsave;
#endif
/* Special-Purpose Registers */
diff -r 32b10ed507f1 -r 7b25f1309eb1 xen/include/asm-ppc/ppc64/config.h
--- a/xen/include/asm-ppc/ppc64/config.h Tue Jun 13 15:00:54 2006 -0400
+++ b/xen/include/asm-ppc/ppc64/config.h Tue Jun 13 15:14:57 2006 -0400
@@ -33,6 +33,7 @@
#define NUM_SLB_ENTRIES 64
#define NUM_FPRS 32
#define HAS_FLOAT 1
+#define HAS_VMX 1
#ifndef __ASSEMBLY__
_______________________________________________
Xen-ppc-devel mailing list
Xen-ppc-devel@xxxxxxxxxxxxxxxxxxx
http://lists.xensource.com/xen-ppc-devel
|
Home