# HG changeset patch
# User yamahata@xxxxxxxxxxxxx
# Date 1197948060 -32400
# Node ID 35c9c479300d4964c5b902c5347d03e096e923d8
# Parent  144d7d5b73551d5451f278f8f02647c85ffb51c3
rearrange IA64_TR_ definitions to use from lower value.
SDM vol2 4.1.1.1 says that
"software should allocate contiguous translation registers starting
at slot 0 and continuing upwards."
PATCHNAME: rearragne_ia64_tr_definitions

Signed-off-by: Isaku Yamahata <yamahata@xxxxxxxxxxxxx>

diff -r 144d7d5b7355 -r 35c9c479300d xen/include/asm-ia64/xenkregs.h
--- a/xen/include/asm-ia64/xenkregs.h	Tue Dec 18 15:44:12 2007 +0900
+++ b/xen/include/asm-ia64/xenkregs.h	Tue Dec 18 12:21:00 2007 +0900
@@ -4,10 +4,11 @@
 /*
  * Translation registers:
  */
-#define IA64_TR_SHARED_INFO	3	/* dtr3: page shared with domain */
-#define	IA64_TR_VHPT		4	/* dtr4: vhpt */
+#define IA64_TR_XEN_HEAP_REGS	3	/* dtr3: xen heap identity mapped regs */
+#define IA64_TR_SHARED_INFO	4	/* dtr4: page shared with domain */
 #define IA64_TR_MAPPED_REGS	5	/* dtr5: vcpu mapped regs */
-#define IA64_TR_XEN_HEAP_REGS	6	/* dtr6: xen heap identity mapped regs */
+#define	IA64_TR_VHPT		6	/* dtr6: vhpt */
+
 #define IA64_DTR_GUEST_KERNEL   7
 #define IA64_ITR_GUEST_KERNEL   2
 /* Processor status register bits: */