RE: [Xen-devel]Question about qemu interrupt deliver.

["Xu, Anthony" <anthony.xu@xxxxxxxxx>]

Keir Fraser write on 2006年11月29日 16:11:
> On 29/11/06 7:57 am, "Xu, Anthony" <anthony.xu@xxxxxxxxx> wrote:
> 
>> 1. Why is the interrupt router table put inside hypervisor other
>> than Qemu? 
>> 
>> 2. Why is the relationship of PCI device interrupt pin to IOAPIC
>>    input pin put inside hypervisor other than Qemu?
> 
> Since the PICs live in Xen it seems cleaner to move interrupt
> steering there too and have a clean device-level interface to device
> models. It also means that this core piece of chipset infrastructure
> is available for use by PCI devices that we may implement in Xen or
> anywhere else outside the qemu-dm process in future, so in this
> respect it is more flexible rather than less. 

Thanks,
This answered the first question.

How about the second one?
#define hvm_pci_intx_gsi(dev, intx)  \
    (((((dev)<<2) + ((dev)>>3) + (intx)) & 31) + 16)

Why this logic is implemented inside hypervisor?

Thanks,
Anthony


> 
>  -- Keir

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