RE: [Xen-ia64-devel][PATCH]Revert back PAL_VM_SUMMARY andPAL_VM_INFO handling

["Xu, Anthony" <anthony.xu@xxxxxxxxx>]

Alex,

>From following vm_info information, we can see domU is running on a weird CPU,
1. L1 TLB is unified, but L2 is spitted.
2. L1 TLB has 128 entries, but L2 only has 1. 
3. TLB insertable page sizes      : 4K 8K 16K 64K 256K 1M 4M 16M 64M 256M 1G 4G 
   TLB purgeable page sizes       : 4K 8K 16K 64K 256K 1M 4M 16M 64M 256M 1G 4G
   But both L1 and L2 only support 16K page size.
...


Why not we get vm_info from physical CPU, and only modify some fields which 
have to be virtualized.
IMO, these features are,
1. Virtual Address Space
2. Size of RR.rid.
3. Number of DTR and ITR,
4. Purge outer loop count and Purge inner loop count.
...



Execute cat /proc/pal/cpu0/vm_info on domU

Physical Address Space         : 44 bits
Virtual Address Space          : 51 bits
Protection Key Registers(PKR)  : 16
Implemented bits in PKR.key    : 16
Hash Tag ID                    : 0x30
Size of RR.rid                 : 18
Supported memory attributes    : WB, UC, UCE, WC, NaTPage

TLB walker                     : implemented
Number of DTR                  : 8
Number of ITR                  : 8
TLB insertable page sizes      : 4K 8K 16K 64K 256K 1M 4M 16M 64M 256M 1G 4G
TLB purgeable page sizes       : 4K 8K 16K 64K 256K 1M 4M 16M 64M 256M 1G 4G
Purge base address             : 0x0000000000000000
Purge outer loop count         : 1
Purge inner loop count         : 1
Purge outer loop stride        : 0
Purge inner loop stride        : 0
TC Levels                      : 2
Unique TC(s)                   : 3

Data/Instruction Translation Cache Level 1:
        Hash sets           : 128
        Associativity       : 1
        Number of entries   : 128
        Flags               : PreferredPageSizeOptimized Unified
        Supported page sizes: 16K
Data Translation Cache Level 2:
        Hash sets           : 1
        Associativity       : 1
        Number of entries   : 1
        Flags               : PreferredPageSizeOptimized
        Supported page sizes: 16K
Instruction Translation Cache Level 2:
        Hash sets           : 1
        Associativity       : 1
        Number of entries   : 1
        Flags               : PreferredPageSizeOptimized
        Supported page sizes: 16K




Execute cat /proc/pal/cpu0/vm_info on native linux OS

Physical Address Space         : 50 bits
Virtual Address Space          : 61 bits
Protection Key Registers(PKR)  : 16
Implemented bits in PKR.key    : 24
Hash Tag ID                    : 0x2
Size of RR.rid                 : 24
Supported memory attributes    : WB, UC, UCE, WC, NaTPage

TLB walker                     : implemented
Number of DTR                  : 32
Number of ITR                  : 32
TLB insertable page sizes      : 4K 8K 16K 64K 256K 1M 4M 16M 64M 256M 1G 4G
TLB purgeable page sizes       : 4K 8K 16K 64K 256K 1M 4M 16M 64M 256M 1G 4G
Purge base address             : 0x0000000000000000
Purge outer loop count         : 1
Purge inner loop count         : 1
Purge outer loop stride        : 0
Purge inner loop stride        : 0
TC Levels                      : 2
Unique TC(s)                   : 4

Data Translation Cache Level 1:
        Hash sets           : 1
        Associativity       : 32
        Number of entries   : 32
        Flags               :
        Supported page sizes: 4K 8K 16K 64K 256K 1M 4M 16M 64M 256M 1G 4G
Instruction Translation Cache Level 1:
        Hash sets           : 1
        Associativity       : 32
        Number of entries   : 32
        Flags               :
        Supported page sizes: 4K 8K 16K 64K 256K 1M 4M 16M 64M 256M 1G 4G
Data Translation Cache Level 2:
        Hash sets           : 1
        Associativity       : 128
        Number of entries   : 128
        Flags               : TCReduction
        Supported page sizes: 4K 8K 16K 64K 256K 1M 4M 16M 64M 256M 1G 4G
Instruction Translation Cache Level 2:
        Hash sets           : 1
        Associativity       : 128
        Number of entries   : 128
        Flags               : TCReduction
        Supported page sizes: 4K 8K 16K 64K 256K 1M 4M 16M 64M 256M 1G 4G



>-----Original Message-----
>From: Alex Williamson [mailto:alex.williamson@xxxxxx]
>Sent: 2006年10月26日 10:05
>To: Xu, Anthony
>Cc: xen-ia64-devel
>Subject: Re: [Xen-ia64-devel][PATCH]Revert back PAL_VM_SUMMARY andPAL_VM_INFO
>handling
>
>On Thu, 2006-10-26 at 09:59 +0800, Xu, Anthony wrote:
>> Revert back PAL_VM_SUMMARY and PAL_VM_INFO handle for VTI domain
>
>  Why?  Thanks,
>
>       Alex

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