On Tue, Sep 20, 2011 at 8:57 PM, Jan Beulich <JBeulich@xxxxxxxx> wrote:
>>>> On 20.09.11 at 12:55, Daniel Castro <evil.dani@xxxxxxxxx> wrote:
>> What I am trying is writing to the xenstore ring, issue the send
>> hypercall, then wait (poll hypercall) for event, then read answer from
>> ring.
>
> That reads as if you do all this from the same thread in the same domain.
> Which might be your problem, particularly if additionally you use the
> same event channel for signaling production and consumption.
Yes you are correct, I have all in the same thread. But I have no
other choice, since this is run inside hvmloader when the BIOS is
being deployed.
>> The waiting is not working, but If I wait enough time, the ring will
>> contain the answer, but apparently I have a problem with my event
>> channel port. So to test this theory I am using event channel status
>> hypercall, and I get:
>> Status 2 (meaning interdomain connected)
>> VCPU 0
>> The Union reports dom 32752 and port 2.
>
> 32752 == DOMID_SELF. And I can't see where the hypercall
> implementation would return DOMID_SELF here.
Sorry I had a coding error, but it is corrected (I did not call the
union correctly, so I ended up calling dom in the main struct).
Anyway here is the output corrected:
Xenbus rings @0xfeffc000, event channel 2
Event Chn 2 Status 2 VCPU 0.
Event is interdomain (2) union dom 983040 union port 42
Thanks,
Daniel
>
>> Right now, there are two things that jump to my mind, first when I
>> issue the poll hypercall the system continues execution, instead of
>> yielding CPU unitl event arrives. If it were never to arrive it should
>> yield infinitely, right?
>
> Without a timeout, yes.
>
>> Second, the bit is never set. Or it is being undone before I can check it.
>
> That would need to be you to undo it.
>
> Jan
>
>
--
+-=====---------------------------+
| +---------------------------------+ | This space intentionally blank
for notetaking.
| | | Daniel Castro, |
| | | Consultant/Programmer.|
| | | U Andes |
+-------------------------------------+
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