x86: Remove timeouts from INIT-SIPI-SIPI sequence when using x2apic. Some of the timeouts are pointless since they're waiting for the ICR to ack the IPI delivery and that doesn't happen on x2apic. The others should be benign (and are suggested in the SDM) but removing them makes AP bringup much more reliable on some test boxes. diff -r e2235fe267eb -r 132dae3ced15 xen/arch/x86/smpboot.c --- a/xen/arch/x86/smpboot.c Thu Jun 23 11:35:55 2011 +0100 +++ b/xen/arch/x86/smpboot.c Thu Jun 23 15:30:08 2011 +0100 @@ -435,29 +435,30 @@ static int wakeup_secondary_cpu(int phys apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, phys_apicid); - Dprintk("Waiting for send to finish...\n"); - timeout = 0; - do { - Dprintk("+"); - udelay(100); - if ( !x2apic_enabled ) + if ( !x2apic_enabled ) + { + Dprintk("Waiting for send to finish...\n"); + timeout = 0; + do { + Dprintk("+"); + udelay(100); send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; - } while ( send_status && (timeout++ < 1000) ); + } while ( send_status && (timeout++ < 1000) ); - mdelay(10); + mdelay(10); - Dprintk("Deasserting INIT.\n"); + Dprintk("Deasserting INIT.\n"); - apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); + apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); - Dprintk("Waiting for send to finish...\n"); - timeout = 0; - do { - Dprintk("+"); - udelay(100); - if ( !x2apic_enabled ) + Dprintk("Waiting for send to finish...\n"); + timeout = 0; + do { + Dprintk("+"); + udelay(100); send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; - } while ( send_status && (timeout++ < 1000) ); + } while ( send_status && (timeout++ < 1000) ); + } /* * Should we send STARTUP IPIs ? @@ -486,22 +487,24 @@ static int wakeup_secondary_cpu(int phys */ apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), phys_apicid); - /* Give the other CPU some time to accept the IPI. */ - udelay(300); + if ( !x2apic_enabled ) + { + /* Give the other CPU some time to accept the IPI. */ + udelay(300); - Dprintk("Startup point 1.\n"); + Dprintk("Startup point 1.\n"); - Dprintk("Waiting for send to finish...\n"); - timeout = 0; - do { - Dprintk("+"); - udelay(100); - if ( !x2apic_enabled ) - send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; - } while ( send_status && (timeout++ < 1000) ); + Dprintk("Waiting for send to finish...\n"); + timeout = 0; + do { + Dprintk("+"); + udelay(100); + send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; + } while ( send_status && (timeout++ < 1000) ); - /* Give the other CPU some time to accept the IPI. */ - udelay(200); + /* Give the other CPU some time to accept the IPI. */ + udelay(200); + } /* Due to the Pentium erratum 3AP. */ if ( maxlvt > 3 )