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Re: [Xen-devel] [PATCH 0 of 6] Fix kexec in Xen (take 3)
| To: | Andrew Cooper <andrew.cooper3@xxxxxxxxxx> |
|---|---|
| Subject: | Re: [Xen-devel] [PATCH 0 of 6] Fix kexec in Xen (take 3) |
| From: | Keir Fraser <keir@xxxxxxx> |
| Date: | Thu, 26 May 2011 10:19:59 +0100 |
| Cc: | "xen-devel@xxxxxxxxxxxxxxxxxxx" <xen-devel@xxxxxxxxxxxxxxxxxxx> |
| Delivery-date: | Thu, 26 May 2011 02:27:18 -0700 |
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| Thread-topic: | [Xen-devel] [PATCH 0 of 6] Fix kexec in Xen (take 3) |
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On 26/05/2011 10:12, "Andrew Cooper" <andrew.cooper3@xxxxxxxxxx> wrote: >> A better reference for APIC behaviour is Chapter 10 of Volume 3A of the >> Intel Software Developer Manual. See 10.4.7.1 particularly. The APIC is >> software disabled on startup -- meaning that the enable bit in the SPIV >> register is clear. That is quite different from *hardware* disable (via the >> APICBASE MSR) which your patch attempts to deal with. In this latter case >> the APIC would be totally shut down and it would not be possible to >> INIT-SIPI the secondary processor. The software disable (via SPIV) is very >> much a semi-disabled state (and disable_local_APIC() already returns an APIC >> to that state). >> >> -- Keir >> > Ok - I will read up on this more, and then I guess I have some code to > change. Yes, please do. Also if you can please try to avoid making crash-specific versions of cleanup/shutdown functions. I would actually rather have a global variable indicating I-am-crashing-on-cpu-x, and have at that from the existing shutdown functions to modify their behaviour. If you can fix that plus curb your impulse to do more to the APIC code than necessary then we have a starting point for further review. -- Keir _______________________________________________ Xen-devel mailing list Xen-devel@xxxxxxxxxxxxxxxxxxx http://lists.xensource.com/xen-devel |
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