The use of this varable was only sensible when the choice for local APIC
mode was between enabled or disabled. Now that x2apic is about, it is
wrong, and causes a protection fault in certain cases when trying to tear
down x2apic mode.
The only place where its use is relevent in the code is in
disable_local_APIC which is very out of date. It has now been updated
to be in line with the MultiProcessor Spec, as well as being able
to successfully shut down from x2apic mode without the possibility of
throwing a protection fault (which leads to a general protection fault).
Signed-off-by: Andrew Cooper <andrew.cooper3@xxxxxxxxxx>
diff -r 8d30fccc0771 -r 17991cc69e88 xen/arch/x86/apic.c
--- a/xen/arch/x86/apic.c Wed May 25 15:10:24 2011 +0100
+++ b/xen/arch/x86/apic.c Wed May 25 15:10:52 2011 +0100
@@ -165,8 +165,6 @@ void __init apic_intr_init(void)
/* Using APIC to generate smp_local_timer_interrupt? */
static bool_t __read_mostly using_apic_timer;
-static bool_t __read_mostly enabled_via_apicbase;
-
int get_physical_broadcast(void)
{
if (modern_apic())
@@ -330,6 +328,8 @@ void disconnect_bsp_APIC(int virt_wire_s
void disable_local_APIC(void)
{
+ u64 msr_contents;
+
clear_local_APIC();
/*
@@ -339,10 +339,39 @@ void disable_local_APIC(void)
apic_write_around(APIC_SPIV,
apic_read(APIC_SPIV) & ~APIC_SPIV_APIC_ENABLED);
- if (enabled_via_apicbase) {
- uint64_t msr_content;
- rdmsrl(MSR_IA32_APICBASE, msr_content);
- wrmsrl(MSR_IA32_APICBASE, msr_content & ~MSR_IA32_APICBASE_ENABLE);
+ /* Always disable the APIC */
+ rdmsrl(MSR_IA32_APICBASE, msr_contents);
+ msr_contents &= ~ ( MSR_IA32_APICBASE_ENABLE | MSR_IA32_APICBASE_EXTD );
+ wrmsrl(MSR_IA32_APICBASE, msr_contents);
+
+ /* If we are the boot processor, stick the local apic back to how we found
+ * it on boot. */
+ if( smp_processor_id() != 0 )
+ {
+
+ switch(apic_boot_mode)
+ {
+ case APIC_MODE_DISABLED:
+ break; /* Nothing to do - we did this above */
+ case APIC_MODE_XAPIC:
+ {
+ msr_contents |= MSR_IA32_APICBASE_ENABLE;
+ wrmsrl(MSR_IA32_APICBASE, msr_contents);
+ break;
+ }
+ case APIC_MODE_X2APIC:
+ {
+ msr_contents |= ( MSR_IA32_APICBASE_ENABLE |
MSR_IA32_APICBASE_EXTD );
+ wrmsrl(MSR_IA32_APICBASE, msr_contents);
+ break;
+ }
+ default:
+ {
+ printk("Hit default case when reverting lapic to boot state on
core #%d\n",
+ smp_processor_id());
+ break;
+ }
+ }
}
}
@@ -874,7 +903,6 @@ static int __init detect_init_APIC (void
wrmsrl(MSR_IA32_APICBASE,
msr_content | MSR_IA32_APICBASE_ENABLE
| APIC_DEFAULT_PHYS_BASE);
- enabled_via_apicbase = 1;
}
}
/*
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