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Re: [Xen-devel] [PATCH][RFC] FPU LWP 0/5: patch description
| To: | Wei Huang <wei.huang2@xxxxxxx>, "'xen-devel@xxxxxxxxxxxxxxxxxxx'" <xen-devel@xxxxxxxxxxxxxxxxxxx> |
|---|---|
| Subject: | Re: [Xen-devel] [PATCH][RFC] FPU LWP 0/5: patch description |
| From: | Keir Fraser <keir.xen@xxxxxxxxx> |
| Date: | Thu, 14 Apr 2011 22:09:59 +0100 |
| Cc: | |
| Delivery-date: | Thu, 14 Apr 2011 14:11:50 -0700 |
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| Thread-topic: | [Xen-devel] [PATCH][RFC] FPU LWP 0/5: patch description |
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On 14/04/2011 21:37, "Wei Huang" <wei.huang2@xxxxxxx> wrote: > The following patches support AMD lightweight profiling. > > Because LWP isn't tracked by CR0.TS bit, we clean up the FPU code to > handle lazy and unlazy FPU states differently. Lazy FPU state (such as > SSE, YMM) is handled when #NM is triggered. Unlazy state, such as LWP, > is saved and restored on each vcpu context switch. To simplify the code, > we also add a mask option to xsave/xrstor function. How much cost is added to context switch paths in the (overwhelmingly likely) case that LWP is not being used by the guest? Is this adding a whole lot of unconditional overhead for a feature that noone uses? -- Keir > Thanks, > -Wei > > > > _______________________________________________ > Xen-devel mailing list > Xen-devel@xxxxxxxxxxxxxxxxxxx > http://lists.xensource.com/xen-devel _______________________________________________ Xen-devel mailing list Xen-devel@xxxxxxxxxxxxxxxxxxx http://lists.xensource.com/xen-devel |
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