On Fri, Apr 01, 2011 at 04:02:36PM +0200, Peter Zijlstra wrote:
> > S0i3 on cpu0 can be entered only after cpu1 is already off-line,
> > among other system hardware dependencies...
> > So it makes no sense to export S0i3 as a c-state on cpu1.
> > When cpu1 is online, the scheduler treats it as a normal SMP.
> Dipankar's reply seems to address this issue well.
I can't find any Moorestown documentation at the Intel site, but
thinking about Len's inputs a bit more, it seems there may
be still a problem asymetry from the scheduler perspective.
If cpu0 or cpu1 either of them can be offlined, there is no
asymetry. If only cpu1 can be offlined, it would mean that
one cpu may be more efficient depending on how we do
cpu offlining for power savings. It gets a bit messy.
Len, what exacty is the significance of offlining here ?
Apart from going to C6, what else is needed in cpu1 for
the chip to go to S0i3 ? Why is idle C6 not enough ?
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