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xen-devel
RE: [Xen-devel] [PATCH 4/5][RFC] lwp: adding support for AMD lightweight
This might be possible. The frequency of MSR read/write inside guest VM will be
less compared with vcpu context switch. I will try it in next spin.
-Wei
-----Original Message-----
From: Jan Beulich [mailto:JBeulich@xxxxxxxxxx]
Sent: Monday, February 14, 2011 10:18 AM
To: Huang2, Wei
Cc: Gang Wei; xen-devel@xxxxxxxxxxxxxxxxxxx; KeirFraser
Subject: RE: [Xen-devel] [PATCH 4/5][RFC] lwp: adding support for AMD
lightweight profiling
>>> On 14.02.11 at 16:55, "Huang2, Wei" <Wei.Huang2@xxxxxxx> wrote:
> No there is no quick way (like TS bit) to keep track LWP state. Here is an
> excerpt from lwp spec:
>
> "LWP does not support the "lazy" state save and restore that is possible for
> floating point and SSE state. It does not interact with the CR0.TS bit.
> Operating systems that support LWP must always do an XSAVE to preserve the
> old thread's LWP context and an XRSTOR to set up the new LWP context. The OS
> can continue to do a lazy switch of the FP and SSE state by ensuring that the
> corresponding bits in EDX:EAX are clear when it executes the XSAVE and XRSTOR
> to handle the LWP context."
I certainly wasn't thinking of CR0.TS, but after reading patch 5 my
question should have been re-phrased into whether the intercept
of the control MSR can't be used for tracking purposes.
Jan
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