exporting patch: # HG changeset patch # User Wei Huang # Date 1294430138 21600 # Node ID cf37822a228e42261c3f536e3447e099e5d85333 # Parent 98d455ef23eed267084c02bf34f2d71d34ff425b Update AMD CPU feature flags 0x80000001:ECX for Xen tools This patch syncs-up AMD CPU feature flags 0x80000001:ECX in libxc with the latest Linux kernel. Signed-off-by: Wei Huang diff -r 98d455ef23ee -r cf37822a228e tools/libxc/xc_cpufeature.h --- a/tools/libxc/xc_cpufeature.h Fri Jan 07 13:37:58 2011 -0600 +++ b/tools/libxc/xc_cpufeature.h Fri Jan 07 13:55:38 2011 -0600 @@ -119,19 +119,24 @@ #define X86_FEATURE_PMM_EN (5*32+ 13) /* PMM enabled */ /* More extended AMD flags: CPUID level 0x80000001, ecx, word 6 */ -#define X86_FEATURE_LAHF_LM (6*32+ 0) /* LAHF/SAHF in long mode */ -#define X86_FEATURE_CMP_LEGACY (6*32+ 1) /* If yes HyperThreading not valid */ -#define X86_FEATURE_SVME (6*32+ 2) /* Secure Virtual Machine */ -#define X86_FEATURE_EXTAPICSPACE (6*32+ 3) /* Extended APIC space */ -#define X86_FEATURE_ALTMOVCR (6*32+ 4) /* LOCK MOV CR accesses CR+8 */ -#define X86_FEATURE_ABM (6*32+ 5) /* Advanced Bit Manipulation */ -#define X86_FEATURE_SSE4A (6*32+ 6) /* AMD Streaming SIMD Extensions-4a */ -#define X86_FEATURE_MISALIGNSSE (6*32+ 7) /* Misaligned SSE Access */ -#define X86_FEATURE_3DNOWPF (6*32+ 8) /* 3DNow! Prefetch */ -#define X86_FEATURE_OSVW (6*32+ 9) /* OS Visible Workaround */ -#define X86_FEATURE_IBS (6*32+ 10) /* Instruction Based Sampling */ -#define X86_FEATURE_SSE5 (6*32+ 11) /* AMD Streaming SIMD Extensions-5 */ -#define X86_FEATURE_SKINIT (6*32+ 12) /* SKINIT, STGI/CLGI, DEV */ -#define X86_FEATURE_WDT (6*32+ 13) /* Watchdog Timer */ +#define X86_FEATURE_LAHF_LM (6*32+ 0) /* LAHF/SAHF in long mode */ +#define X86_FEATURE_CMP_LEGACY (6*32+ 1) /* If yes HyperThreading not valid */ +#define X86_FEATURE_SVM (6*32+ 2) /* Secure virtual machine */ +#define X86_FEATURE_EXTAPIC (6*32+ 3) /* Extended APIC space */ +#define X86_FEATURE_CR8_LEGACY (6*32+ 4) /* CR8 in 32-bit mode */ +#define X86_FEATURE_ABM (6*32+ 5) /* Advanced bit manipulation */ +#define X86_FEATURE_SSE4A (6*32+ 6) /* SSE-4A */ +#define X86_FEATURE_MISALIGNSSE (6*32+ 7) /* Misaligned SSE mode */ +#define X86_FEATURE_3DNOWPREFETCH (6*32+ 8) /* 3DNow prefetch instructions */ +#define X86_FEATURE_OSVW (6*32+ 9) /* OS Visible Workaround */ +#define X86_FEATURE_IBS (6*32+10) /* Instruction Based Sampling */ +#define X86_FEATURE_XOP (6*32+11) /* extended AVX instructions */ +#define X86_FEATURE_SKINIT (6*32+12) /* SKINIT/STGI instructions */ +#define X86_FEATURE_WDT (6*32+13) /* Watchdog timer */ +#define X86_FEATURE_LWP (6*32+15) /* Light Weight Profiling */ +#define X86_FEATURE_FMA4 (6*32+16) /* 4 operands MAC instructions */ +#define X86_FEATURE_NODEID_MSR (6*32+19) /* NodeId MSR */ +#define X86_FEATURE_TBM (6*32+21) /* trailing bit manipulations */ +#define X86_FEATURE_TOPOEXT (6*32+22) /* topology extensions CPUID leafs */ #endif /* __LIBXC_CPUFEATURE_H */ diff -r 98d455ef23ee -r cf37822a228e tools/libxc/xc_cpuid_x86.c --- a/tools/libxc/xc_cpuid_x86.c Fri Jan 07 13:37:58 2011 -0600 +++ b/tools/libxc/xc_cpuid_x86.c Fri Jan 07 13:55:38 2011 -0600 @@ -97,11 +97,11 @@ /* Filter all other features according to a whitelist. */ regs[2] &= ((is_64bit ? bitmaskof(X86_FEATURE_LAHF_LM) : 0) | bitmaskof(X86_FEATURE_CMP_LEGACY) | - bitmaskof(X86_FEATURE_ALTMOVCR) | + bitmaskof(X86_FEATURE_CR8_LEGACY) | bitmaskof(X86_FEATURE_ABM) | bitmaskof(X86_FEATURE_SSE4A) | bitmaskof(X86_FEATURE_MISALIGNSSE) | - bitmaskof(X86_FEATURE_3DNOWPF)); + bitmaskof(X86_FEATURE_3DNOWPREFETCH)); regs[3] &= (0x0183f3ff | /* features shared with 0x00000001:EDX */ (is_pae ? bitmaskof(X86_FEATURE_NX) : 0) | (is_64bit ? bitmaskof(X86_FEATURE_LM) : 0) | @@ -422,7 +422,7 @@ clear_bit(X86_FEATURE_PAGE1GB, regs[3]); clear_bit(X86_FEATURE_RDTSCP, regs[3]); - clear_bit(X86_FEATURE_SVME, regs[2]); + clear_bit(X86_FEATURE_SVM, regs[2]); clear_bit(X86_FEATURE_OSVW, regs[2]); clear_bit(X86_FEATURE_IBS, regs[2]); clear_bit(X86_FEATURE_SKINIT, regs[2]);