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[Xen-devel] Re: Comments on Xen bug 1732

>>> On 31.01.11 at 09:52, Haitao Shan <maillists.shan@xxxxxxxxx> wrote:
>> > BTW: I vaguely recall that MSI-X table base might not be the first page
>> of
>> > the corresponding BAR register.
>> While I agree that the code is lacking the use of
>> msix_table_offset_reg(), I would question what else would be
>> in the range supplied by the BAR, as the specification allows
>> only MSI-X table and PBA to share a BAR.
> This is what I copied from PCI spec 3.0. I don't see that the spec only
> allows the two to be shared.
> -----------------------------PCI----------
> To enable system software to map MSI-X structures onto different processor
> pages for
> improved access control, it is recommended that a function dedicate separate
> Base Address
> registers for the MSI-X Table and MSI-X PBA, or else provide more than the
> minimum
> required isolation with address ranges.
> If dedicated separate Base Address registers is not feasible, it is
> recommended that a
> function dedicate a single Base Address register for the MSI-X Table and
> If a dedicated Base Address register is not feasible, it is recommended that
> a function isolate
> the MSI-X structures from the non-MSI-X structures with aligned 8 KB ranges
> rather than
> the mandatory aligned 4 KB ranges.
> --------------------------spec---------------

Sorry, it should have been *page* instead of *BAR*. I certainly
can propose a fix to the not-at-offset-zero part of the problem,
but the VF (SR-IOV) specific part (i.e. the determination which
of the warnings can be dropped safely) should be done by
someone more familiar with all aspects of it.


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