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RE: [Xen-devel] xm save + restore crashes Windows 200832-bit(4.0.2-rc2-p

To: "Tim Deegan" <Tim.Deegan@xxxxxxxxxx>
Subject: RE: [Xen-devel] xm save + restore crashes Windows 200832-bit(4.0.2-rc2-pre) (AMD only)
From: "James Harper" <james.harper@xxxxxxxxxxxxxxxx>
Date: Wed, 26 Jan 2011 09:25:17 +1100
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Thread-index: Acu83koGKYQieF6RSdON1Mbx9Y2VHwAAAjLQ
Thread-topic: [Xen-devel] xm save + restore crashes Windows 200832-bit(4.0.2-rc2-pre) (AMD only)
> >
> > Just to clarify, in the restore path I print the values to be saved
> > the segment registers, then I read the segment registers and print
> > values that are in them. They aren't the same. Doesn't that sound
like a
> > problem on the restore side?
> That would depend on how you read the values after the restore - the
> patch is for a bug that I think is causing svm_get_segment_register()
> corrupt the vmcb if it's called before the vcpu is first scheduled
> to return the corrupted values).

I see. I just tested and while I still get the crash, all the segment
registers are now correct after applying your patch.

The only thing I can see that's different now is the MTRR's.


--- before      2011-01-26 09:16:19.030666000 +1100
+++ after       2011-01-26 09:21:13.374664075 +1100
@@ -1,4 +1,4 @@
-HVM save record for domain 4
+HVM save record for domain 6
 Entry 0: type 1 instance 0, length 24
      Header: magic 0x54381286, version 1
              Xen changeset 0
@@ -34,7 +34,7 @@
       MSR flags 0xffffffffffffffff  lstar 0x0000000000000000
            star 0x0000000000000000  cstar 0x0000000000000000
          sfmask 0x0000000000000000   efer 0x0000000000000800
-            tsc 0x000000172cbec19e
+            tsc 0x0000005866dd3e1f
           event 0x00000000 error 0x00000000
     FPU:    fcw 0x027f fsw 0x0000
             ftw 0x00 (0x00) fop 0x0000
@@ -185,11 +185,11 @@
                rd_state 0, wr_state 0, wr_latch 0, rw_mode 0
                mode 0xff, bcd 0, gate 0x1
 Entry 11: type 11 instance 0, length 16
-    RTC: regs 0x16 0x00 0x16 0x00 0x09 0x00 0x03 0x26
+    RTC: regs 0x12 0x00 0x21 0x00 0x09 0x00 0x03 0x26
               0x01 0x11 0x2a 0x42 0x00 0x80, index 0x0c
 Entry 12: type 12 instance 0, length 1048
     HPET: capability 0xf424008086a201 config 0
-          isr 0 counter 0x1f65b81fc
+          isr 0 counter 0x43a264ae0
           timer0 config 0xf0000000000030 cmp 0
           timer0 period 0 fsb 0
           timer1 config 0xf0000000000030 cmp 0
@@ -200,8 +200,8 @@
     ACPI PM: TMR_VAL 0x19b239a8, PM1a_STS 0x0, PM1a_EN 0x321
 Entry 14: type 14 instance 0, length 240
     MTRR: PAT 0x7010600070106, cap 0x508, default 0xc06
-          var 0 0x00000000f0000000 0x000000fff8000800
-          var 1 0x00000000f8000000 0x000000fffc000800
+          var 0 0x00000000f0000000 0x0000000000000000
+          var 1 0x00000000f8000000 0x0000000000000000
           var 2 0x0000000000000000 0x0000000000000000
           var 3 0x0000000000000000 0x0000000000000000
           var 4 0x0000000000000000 0x0000000000000000

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