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Re: [Xen-devel] [RFC PATCH 0/2] ASID: Flush by ASID

To: Tim Deegan <Tim.Deegan@xxxxxxxxxx>
Subject: Re: [Xen-devel] [RFC PATCH 0/2] ASID: Flush by ASID
From: Wei Wang2 <wei.wang2@xxxxxxx>
Date: Wed, 12 Jan 2011 13:41:10 +0100
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Hi Tim,
Flush by ASID provides more flexible control of tlb flushing. The most 
advantage is to allow hypervisor to flush tagged tlb selectively. Using this 
feature, HV is able to flush tlb entries associated with a guest VM directly 
instead of allocating a new asid . The whole tlb flush will also be reduced 
by reducing asid allocation.  

So far, we did not measure drastic performance improvement in testing with 
kernbench and X11perf. Actually, we found out that, reducing tlb flushes 
accompanying with vmrun does not improve performance very much. 
we sent out a patch to optimize hvm_flush_guest_tlbs last week, which reduces 
over 90% tlb flushes for vmrun, and we even cannot see signification speedup 
with it. Maybe, the latency of vmrun is too big so that the overhead of tlb 
flush is negligible?


On Wednesday 12 January 2011 11:17:00 Tim Deegan wrote:
> At 17:55 +0000 on 11 Jan (1294768552), Wei Wang2 wrote:
> > Future AMD SVM supports a new feature called flush by ASID. The idea is
> > to allow CPU to flush TLBs associated with the ASID assigned to guest VM.
> > So hypervisor doesn't have to reassign a new ASID in order to flush
> > guest's VCPU.  Please review it.
> What advantage does the new system have?  Intuitively it seems like it
> might be a tiny bit fairer and a tiny bit faster (by explicitly flushing
> instead of relying on LRO) but I'm not convinced that it will be visible
> in macro-benchmarks.  Have you measured it?
> Cheers,
> Tim.
> > Thanks,
> > Wei
> >
> > Signed-off-by: Wei Huang <wei.huang2@xxxxxxx>
> > Signed-off-by: Wei Wang <wei.wang2@xxxxxxx>
> > --
> > Advanced Micro Devices GmbH
> > Sitz: Dornach, Gemeinde Aschheim,
> > Landkreis München Registergericht München,
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