Re: [Xen-devel] xen 4 only seeing one keyboard and mouse

[Konrad Rzeszutek Wilk <konrad.wilk@xxxxxxxxxx>]

On Mon, Aug 16, 2010 at 06:33:54PM -0400, Konrad Rzeszutek Wilk wrote:
> On Mon, Aug 16, 2010 at 10:05:58PM +0100, M A Young wrote:
> > On Mon, 16 Aug 2010, Konrad Rzeszutek Wilk wrote:
> > 
> > >There are a couple of things we can try:
> > >- Compare this with the output from Xen 3.4 and see if the IOAPIC lines
> > >  are different. Especially if these:
> > >(XEN) IOAPIC[0]: Set PCI routing entry (2-12 -> 0x78 -> IRQ 12 Mode:0 
> > >Active:0)
> > >(XEN) IOAPIC[0]: Set PCI routing entry (2-1 -> 0x28 -> IRQ 1 Mode:0 
> > >Active:0
> > >
> > >are different. I think that previous to Xen 4, the pv-ops kernel could
> > >not set the IOAPIC entries below pin 16, so you would not see them and
> > >instead it would have these programmed:
> > >(XEN)  01 001 01  0    0    0   0   0    1    1    28
> > >(XEN)  0c 001 01  0    0    0   0   0    1    1    78
> > >
> > >Which is OK, as the trigger and polarity look to be correct.
> > 
> > Logs attached as dmesg.xen3 and xm.xen3
> 
> Cool. So this is what I see
> 
> (XEN)  NR Log Phy Mask Trig IRR Pol Stat Dest Deli Vect:      |       (XEN)  
> NR Log Phy Mask Trig IRR Pol Stat Dest Deli Vect:   
> (XEN)  00 000 00  1    0    0   0   0    0    0    00         (XEN)  00 000 
> 00  1    0    0   0   0    0    0    00
> (XEN)  01 001 01  0    0    0   0   0    1    1    20       | (XEN)  01 001 
> 01  0    0    0   0   0    1    1    28
> (XEN)  02 001 01  0    0    0   0   0    1    1    F0         (XEN)  02 001 
> 01  0    0    0   0   0    1    1    F0
> (XEN)  03 001 01  0    0    0   0   0    1    1    28       | (XEN)  03 001 
> 01  0    0    0   0   0    1    1    30
> (XEN)  04 001 01  0    0    0   0   0    1    1    30       | (XEN)  04 001 
> 01  0    0    0   0   0    1    1    38
> (XEN)  05 001 01  0    0    0   0   0    1    1    38       | (XEN)  05 001 
> 01  0    0    0   0   0    1    1    40
> (XEN)  06 001 01  0    0    0   0   0    1    1    40       | (XEN)  06 001 
> 01  0    0    0   0   0    1    1    48
> (XEN)  07 001 01  0    0    0   0   0    1    1    48       | (XEN)  07 001 
> 01  0    0    0   0   0    1    1    50
> (XEN)  08 001 01  0    0    0   0   0    1    1    50       | (XEN)  08 001 
> 01  0    0    0   0   0    1    1    58
> (XEN)  09 001 01  1    1    0   0   0    1    1    58       | (XEN)  09 001 
> 01  1    1    0   0   0    1    1    60
> (XEN)  0a 001 01  0    0    0   0   0    1    1    60       | (XEN)  0a 001 
> 01  0    0    0   0   0    1    1    68
> (XEN)  0b 001 01  0    0    0   0   0    1    1    68       | (XEN)  0b 001 
> 01  0    0    0   0   0    1    1    70
> (XEN)  0c 001 01  0    0    0   0   0    1    1    70       | (XEN)  0c 001 
> 01  0    0    0   0   0    1    1    78
> (XEN)  0d 001 01  0    0    0   0   0    1    1    78       | (XEN)  0d 001 
> 01  0    0    0   0   0    1    1    88
> (XEN)  0e 001 01  0    0    0   0   0    1    1    88       | (XEN)  0e 001 
> 01  0    0    0   0   0    1    1    90
> (XEN)  0f 001 01  0    0    0   0   0    1    1    90       | (XEN)  0f 001 
> 01  0    0    0   0   0    1    1    98
> (XEN)  10 000 00  1    0    0   0   0    0    0    00         (XEN)  10 000 
> 00  1    0    0   0   0    0    0    00
> ..
> Left column is 3.4, right is 4.0.
> 
> The one thing that is odd is that in 4.0 we start with vector 0x28 while
> in 3.4 it is with 0x20.
> 
> It looks as if one vector is getten eaten. But that should not be such
> an issue as the internal mapping of vector->irq is still proper...

This looks like a one-offset bug. On a related note this
might be the same as when my irq delivery goes haywire under load
and the IRQ delivery is put on another CPU but that whole process
looks to be taking 10-20 seconds.

When did you start observing this? It is a bit hard to bisect code
between 3.4. and 4.0. Did it work with 4.0?

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