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[Xen-devel] [Patch] cpu synchronization while doing MTRR register update

To: Keir Fraser <keir.fraser@xxxxxxxxxxxxx>
Subject: [Xen-devel] [Patch] cpu synchronization while doing MTRR register update
From: Nitin A Kamble <nitin.a.kamble@xxxxxxxxx>
Date: Tue, 04 Aug 2009 11:26:21 -0700
Cc: asit.k.mallick@xxxxxxxxx, xen-devel@xxxxxxxxxxxxxxxxxxx, suresh.b.siddha@xxxxxxxxx
Delivery-date: Tue, 04 Aug 2009 11:25:56 -0700
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The current Xen code does not synchronize all the cpus while
initializing MTRR registers when a cpu comes up. 

As per IA32 SDM vol 3: Section: 10.11.8 MTRR Considerations in MP
Systems, all the processors should be synchronized while updating MTRRs.

Processors starting with westmere are caching VMCS data for better VMX
performance. These processors also has Hyper-threading support. With
hyper-threading, when one thread's cache is disabled, it also disables
cache for the sibling threads. And MTRR register updating procedure
involves cache disabling. So if cpus are not synchronized, updating MTRR
registers on a thread, results in the VMCS data from sibling threads
becoming inaccessible, and it causes system failure.

With this patch while updating the MTRR registers, all the cpus are
synchronized as per the IA32 SDM. Also at the boot time and resume time
when multiple cpus are brought up, an optimization is added to delay the
MTRR initialization until all the cpus are up, to avoid multiple times
cpu synchronization.

Signed-Off-By: Nitin A Kamble <nitin.a.kamble@xxxxxxxxx>
Signed-Off-By: Suresh B Siddha <suresh.b.siddha@xxxxxxxxx>
Signed-Off-By: Asit K Mallick <asit.k.mallick@xxxxxxxxx>

 arch/x86/acpi/suspend.c  |    2 -
 arch/x86/cpu/common.c    |    2 -
 arch/x86/cpu/mtrr/main.c |   57 +++++++++++++++++++++++++++++---------
 arch/x86/smpboot.c       |    6 ++++
 include/asm-x86/mtrr.h   |    4 +++
 5 files changed, 56 insertions(+), 15 deletions(-)

Thanks & Regards,
Linux Open Source Technology Center, Intel Corporation
The Mind is like a parachute; it works much better when it's open.

Attachment: mtrr_update_cpu_synchronization_r1.diff
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