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[Xen-devel] [PATCH 0/3] save/restore PCI configuration space in pciback.

To: Keir Fraser <keir.fraser@xxxxxxxxxxxxx>, Ian Jackson <Ian.Jackson@xxxxxxxxxxxxx>, Kouya Shimura <kouya@xxxxxxxxxxxxxx>, xen-devel@xxxxxxxxxxxxxxxxxxx
Subject: [Xen-devel] [PATCH 0/3] save/restore PCI configuration space in pciback.
From: Yuji Shimada <shimada-yxb@xxxxxxxxxxxxxxx>
Date: Wed, 22 Apr 2009 11:11:51 +0900
Delivery-date: Tue, 21 Apr 2009 19:12:22 -0700
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This series of patches enables saving/restoring PCI configuration
space in pciback.

Xend saves/restores PCI configuration space on current Xen. But it's
not better place to save/restore. Because devices should be configured
by device driver.
And Shimura-san's D-state problem will be resolved with this patch.
Because I modify the timing of saving/restoring configuration space
like below.

  When pciback is bound to devices.
   - Pciback saves configuration space.

  When pciback is unbound to devices.
   - Pciback restores configuration space.

  When guest OS boots or a device is hotadded.
   - Pciback restores configuration space.
   - Pciback changes state of backend device to Initialised/Reconfigured.
   - Xend waits for the transition to Initialised/Reconfigured.

  When guest OS shutdowns or a device is hotremoved.
   - Pciback restores configuration space.
   - Xend resets devices.
     * If D-state of the device is not D0, the state is changed to D0
       before resetting the device.
   - Xend deassigns devices.

  * Essentially, devices should be reset before configuration space is
    restored. But it needs big modifications. Applying these patches,
    configuration space is restored when guest OS boots, a device is
    hotadded or pciback is unbound. So it has no matter.

The following registers are saved/restored by pciback.

  Configuration Space
   - Base Address Register set
   - Cache-line size Register
   - Latency timer Register
   - Enable SERR Bit / Enable PERR Bit in Control Register
   - Device Control Register (PCI Express Capability)
   - Link Control Register (PCI Express Capability)
   - Device Control 2 Register (PCI Express Capability)
   - Link Control 2 Register (PCI Express Capability)

   - Uncorrectable Error Mask Register
   - Uncorrectable Error Severity Register
   - Correctable Error Mask Register
   - Advanced Error Capabilities and Control Register

Yuji Shimada

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