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RE: [Xen-devel] Time skew on HP DL785 (and possibly other boxes)

To: Dan Magenheimer <dan.magenheimer@xxxxxxxxxx>, "Xen-Devel (E-mail)" <xen-devel@xxxxxxxxxxxxxxxxxxx>
Subject: RE: [Xen-devel] Time skew on HP DL785 (and possibly other boxes)
From: "Tian, Kevin" <kevin.tian@xxxxxxxxx>
Date: Wed, 1 Apr 2009 06:48:21 +0800
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Thread-topic: [Xen-devel] Time skew on HP DL785 (and possibly other boxes)
>From: Dan Magenheimer [mailto:dan.magenheimer@xxxxxxxxxx] 
>Sent: 2009年4月1日 6:08
>
>> >This box uses 8 quad-core AMD chips connected via
>> >hypertransport.  BUT each chip is on a separate motherboard.
>> >On this system hypertransport is fast and cross-node
>> >memory accesses are fast enough so that these NUMA systems
>> >need not behave like NUMA systems from a memory access
>> >perspective.  So Xen just views the system as a 32-cpu box
>> >(other than some code in the memory allocator that tries
>> >to allocate near-memory where possible, but silently falls
>> >back to far-memory if necessary) and guest vcpus migrate
>> >freely between the nodes.  (Correct?)
>>
>> Then instead user'd better to enable NUMA aware bits with Xen which
>> imposes some affinity limitation but looks a reasonable model
>> on large
>> scale system.
>>
>> Thanks,
>> Kevin
>
>Hi Kevin --
>
>Are you suggesting that only NUMA-aware guests should be
>run on systems like this?  If not, what do you mean by
>"NUMA aware bits"?
>

No. I meant the physical NUMA features in Xen. IIRC, once NUMA support is
turned on in Xen (by "numa" boot option), one guest is limited in one node
automatically, meaning both cpu affinity only matching to that node and also
memory allocated locally within that node. 

Thanks,
Kevin
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