>From: Jan Beulich [mailto:jbeulich@xxxxxxxxxx]
>Sent: 2009年3月31日 18:55
>
>>>> "Tian, Kevin" <kevin.tian@xxxxxxxxx> 31.03.09 12:21 >>>
>>BTW, another question comes when I'm clearing the code.
>>in load_segments, fs/gs base MSRs are only updated for non 32-on-64
>>domain. I guess that it's just for performance reason as 32bit guest
>>doesn't require to switch gs base. I want to get your confirmation
>>since in current low level context S3 resume code, we always restore
>>those base MSRs even for 32-on-64 case.
>
>Correct - your code isn't performance sensitive, so keeping it
>simple is
>probably preferable. load_segments() sits in the context
>switch code, and
>thus it tries to avoid things not needed for a particular guest.
>
Thanks. After recovering those 3 SYSENTER MSRs, now 32-on-64
S3 could succeeds several times which is a big step. However there
seems to be some other instability issues to cause machine
occasionally reboot after more S3 actions. Both screen and serial
port is dark and thus no more info is available. We'll continue to dig out
the exact reason. But this shouldn't prevent sending out this
reasonable fix anyway.
Thanks,
Kevin
-----
Enable S3 for 32bit dom0 on 64bit Xen
Three SYSENTER MSRs should be taken care of at save/restore BSP context,
or else 32bit dom0 rejects working after S3 resume. Thanks for Jan's help to
find this missing part.
Signed-off-by Guanqun Lu <guanqun.lu@xxxxxxxxx>
Signed-off-by Kevin Tian <kevin.tian@xxxxxxxxx>
diff -r e152892a0b1e xen/arch/x86/acpi/suspend.c
--- a/xen/arch/x86/acpi/suspend.c Tue Mar 31 10:21:55 2009 +0800
+++ b/xen/arch/x86/acpi/suspend.c Tue Mar 31 19:06:08 2009 +0800
@@ -16,6 +16,7 @@
#if defined(CONFIG_X86_64)
static unsigned long saved_lstar, saved_cstar;
+static unsigned long saved_sysenter_esp, saved_sysenter_eip;
#endif
void save_rest_processor_state(void)
@@ -26,6 +27,8 @@
#if defined(CONFIG_X86_64)
rdmsrl(MSR_CSTAR, saved_cstar);
rdmsrl(MSR_LSTAR, saved_lstar);
+ rdmsrl(MSR_IA32_SYSENTER_ESP, saved_sysenter_esp);
+ rdmsrl(MSR_IA32_SYSENTER_EIP, saved_sysenter_eip);
#endif
}
@@ -41,6 +44,11 @@
wrmsrl(MSR_CSTAR, saved_cstar);
wrmsr(MSR_STAR, 0, (FLAT_RING3_CS32<<16) | __HYPERVISOR_CS);
wrmsr(MSR_SYSCALL_MASK, EF_VM|EF_RF|EF_NT|EF_DF|EF_IE|EF_TF, 0U);
+
+ /* Recover sysenter MSRs */
+ wrmsrl(MSR_IA32_SYSENTER_ESP, saved_sysenter_esp);
+ wrmsrl(MSR_IA32_SYSENTER_EIP, saved_sysenter_eip);
+ wrmsr(MSR_IA32_SYSENTER_CS, __HYPERVISOR_CS, 0);
#else /* !defined(CONFIG_X86_64) */
if ( supervisor_mode_kernel && cpu_has_sep )
wrmsr(MSR_IA32_SYSENTER_ESP, &init_tss[smp_processor_id()].esp1, 0);
32-on-64-s3.patch
Description: 32-on-64-s3.patch
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