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Re: [Xen-devel] pv_ops dom0 clock only runs under load

To: Jeremy Fitzhardinge <jeremy@xxxxxxxx>
Subject: Re: [Xen-devel] pv_ops dom0 clock only runs under load
From: Milan Holzäpfel <listen@xxxxxxxx>
Date: Fri, 6 Mar 2009 21:46:49 +0100
Cc: Milan Holzäpfel <mail@xxxxxxxx>, xen-devel@xxxxxxxxxxxxxxxxxxx
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On Thu, 05 Mar 2009 21:41:44 -0800
Jeremy Fitzhardinge <jeremy@xxxxxxxx> wrote:

> Milan Holzäpfel wrote:
> 
> > The clock only seems to run if the system is under load (e.g. run
> > "while true; do echo -n; done" in a shell).  
> > With the CPU loaded and the clock running everything seems to work
> > quite well (hard disk and network access, that is.)
> >
> > Changing the "xen" clocksource to "tsc" via sysfs didn't make a
> > difference.  Enabling or disabling the "tickless" option doesn't make a
> > difference either. 
> >   
> 
> That's pretty mysterious; it does suggest your cpu's tsc is not ticking.

Excerpt from the dmesg (2.6.29 pvops with / without Xen)

[    4.870697] Marking TSC unstable due to TSC halts in idle

Saw it scrolling by

> Some questions:
> 
>    1. does it work OK with 2.6.18 or other dom0 kernels?

Yes. 2.6.18.8 from the hg repo works fine. 

>    2. what clocksource does the kernel choose when you boot native?

hpet (both 2.6.29 without Xen and 2.6.18 without Xen)

>    3. what does /proc/cpuinfo contain?

Under 2.6.29/Xen:

processor       : 0
vendor_id       : GenuineIntel
cpu family      : 6
model           : 13
model name      : Intel(R) Pentium(R) M processor 1.73GHz
stepping        : 8
cpu MHz         : 1729.018
cache size      : 2048 KB
fdiv_bug        : no
hlt_bug         : no
f00f_bug        : no
coma_bug        : no
fpu             : yes
fpu_exception   : yes
cpuid level     : 2
wp              : yes
flags           : fpu de tsc msr pae cx8 apic mtrr cmov clflush acpi mmx fxsr 
sse sse2 ss up est hypervisor
bogomips        : 3458.03
clflush size    : 64
power management:

>    4. what does /proc/interrupts contain?

Under 2.6.29/Xen:

           CPU0       
  1:        361  xen-pirq-pirq      i8042
  8:          0  xen-pirq-pirq      rtc0
  9:        148  xen-pirq-pirq      acpi
 12:          9  xen-pirq-pirq      i8042
 14:         28  xen-pirq-pirq      ata_piix
 15:          0  xen-pirq-pirq      ata_piix
 22:       2230  xen-pirq-pirq      eth0
 24:       9300   xen-dyn-virq      timer0
 25:          0   xen-dyn-ipi       spinlock0
 26:          0   xen-dyn-ipi       resched0
 27:          0   xen-dyn-ipi       callfunc0
 28:          0   xen-dyn-virq      debug0
 29:          0   xen-dyn-ipi       callfuncsingle0
 30:          0   xen-dyn-event     xenbus
NMI:          0   Non-maskable interrupts
LOC:          0   Local timer interrupts
CNT:          0   Performance counter interrupts
RES:          0   Rescheduling interrupts
CAL:          0   Function call interrupts
TLB:          0   TLB shootdowns
SPU:          0   Spurious interrupts
ERR:          0
MIS:          0

>    5. are there any power management options in the bios you could try
>       turning on/off?

I turned both "Intel SpeedStep" and "CPU Power Saving Mode" off, but it
didn't change anything (2.6.29 with / without Xen)

> > Output is from netconsole, so some messages might have got lost.  I
> > piped the output through "sort". 
> >   
> Why?

Initially I thought packets had got reordered because the indicated
time jumped backwards in one place.  (UDP packets travelling across a
router and WiFi connectiion).  I replaced the connection with direct
ethernet, and saw that indeed no reordering hat taken place.  Packet
loss shouldn't be an issue now too. 


By the way, I booted the 2.6.29 pvops enabled kernel without Xen and
the tsc timesource only increments when the CPU was loaded, too.  On
2.6.18 (without Xen) it worked normally (also with the BIOS options
enabled).

Also, the jiffies timesource seems somewhat broken.  Setting it under
the 2.6.29 pvops kernel without Xen made the clock stop completely
(also when under load).  It couldn't be changed back to hpet anymore. 

I will try whether disabling kernel stuff (there is something called
"cpuidle" compiled in) makes the tsc clocksource work again. 

Let me know if you need further information etc. and thanks for your
support. 

Regards,
Milan


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