RE: [Xen-devel] TPR write optimization (even improves 2003 sp2)

["James Harper" <james.harper@xxxxxxxxxxxxxxxx>]

> > From memory, there is a register somewhere that says what the
highest
> > interrupt level that is currently blocked is... I'll look at that.
This
> > doesn't actually sound that hard...
> 
> An interrupt is delivered if:
>   highest_prio(IRR) > max(highest_prio(ISR), TPR).
> 
> Where highest_prio() is based on a backwards bitmap scan.
> 
> If you go down the route of setting a TPR threshold for vmexit, that
would
> be (hp = highest_prio):
>   TPR_thresh = ((hp(IRR) > hp(ISR)) && (hp(IRR) < TPR)) ? hp(IRR) : 0
> 
> Where VMEXIT occurs if TPR is updated to a value less than the
threshold.
> 

I really need to get xentrace working... if there are lots of reads and
writes to the IRR and ISR registers that all involve VMEXIT's then it
may well be worth mapping the entire APIC register range into the DomU's
memory space (somehow).

Otherwise I can make sure that each write to IRR and ISR (by xen or
domU) gets echo's into DomU's memory in such a form that I can calculate
the value of TPR_thresh that you have given above in my kernel patch and
VMEXIT when necessary from there...

I think I should figure out why xentrace isn't telling me what I want to
know as there are too many conditionals at the moment to know what the
right solution is...

James


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