RE: [Xen-devel] Re: [PATCH] CPUIDLE: revise tsc-save/restore toavoid big tsc skew between cpus

["Jan Beulich" <jbeulich@xxxxxxxxxx>]

>>> "Wei, Gang" <gang.wei@xxxxxxxxx> 16.12.08 03:26 >>>
>Below 't' key outputs are gotten in the extreme case: pin all dom0 & guest 
>vcpus on cpu1 & execute cmd 'while true; do a=1; done'
>within one guest.
>The largest stime skew is ~40us, largest cycles skew is ~100,000 ticks(~40us). 
>The normal idle case skew is quite small (~xxxns).
>
>(XEN) Synced stime skew: max=39662ns avg=8038ns samples=850 current=326ns
>(XEN) Synced cycles skew: max=100475 avg=20368 samples=850 current=825
>...
>(XEN) Synced stime skew: max=39750ns avg=16958ns samples=3954 current=30667ns
>(XEN) Synced cycles skew: max=100708 avg=42967 samples=3954 current=77696
>...
>(XEN) Synced stime skew: max=39750ns avg=17318ns samples=4544 current=22981ns
>(XEN) Synced cycles skew: max=100708 avg=43880 samples=4544 current=58225

Is the average continuing to grow over larger periods of time? I would have
expected it to converge rather than increase as a proof of it being a long
term solution.

Jan


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