If I'm not wrong, Bochs emulates SSE/MMX instructions and qemu uses
dynamic translation. Does this mean that I use SSE/MMX emulation code
from Bochs to put under x86_emulate? or am I missing something?
Thanks.
On Wed, Nov 5, 2008 at 5:34 AM, Ashish Bijlani <ashish.bijlani@xxxxxxxxx> wrote:
> Hi Andre,
>
> You are absolutely right. All hardware virtualization capable machines
> have recent simd technology built-in. However, I'm just trying to
> evaluate a case when HVM guests rely on the virtual hardware platform
> and not on the actual hardware platform. Precisely, what would be the
> performance gain/loss if hypervisor has to emulate the functionality.
>
> -Ashish
>
> On Wed, Nov 5, 2008 at 4:59 AM, Andre Przywara <andre.przywara@xxxxxxx> wrote:
>> Ashish Bijlani wrote:
>>>
>>> Hi,
>>>
>>> I want to emulate mmx/sse for hvm guests when applications inside hvm
>>> guests are compiled for mmx/sse but the underlying hardware doesn't
>>> support mmx/sse.
>>
>> First: HVM guests require a virtualization capable processor. AFAIK all
>> these processors support at least SSE2 (if not SSE3). So why do you want to
>> emulate these instructions?
>> Second: Applications should check the CPUID bit before using instruction set
>> extension. So, if the host processor does not support MMX/SSE, the guest
>> shouldn't see this bit, too. And I doubt that you are faster with emulating
>> SSE compared to legacy x87-FPU executed natively.
>>
>> So, what is the use-case of your proposal? Or am I missing something here?
>>
>> Regards,
>> Andre.
>>
>>> What is the best place to do this? i'm looking at
>>>
>>> x86_emulate but i dunno if that is the best place to put the emulation
>>> layer. any suggestions?? also, currently movq emulation is present in
>>> x86_emulate for handling mmio. however, i realized that get_fpu fails
>>> if the hardware doesn't have mmx capability. is it true or am i
>>> missing something here?
>>>
>>> Thanks,
>>> Ashish
>>
>> --
>> Andre Przywara
>> AMD-OSRC (Dresden)
>> Tel: x84917
>>
>>
>
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