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RE: [Xen-devel] [Patch] x86: enforce strict memory order for x2apic

To: 'Jan Beulich' <jbeulich@xxxxxxxxxx>, "xen-devel@xxxxxxxxxxxxxxxxxxx" <xen-devel@xxxxxxxxxxxxxxxxxxx>
Subject: RE: [Xen-devel] [Patch] x86: enforce strict memory order for x2apic
From: "Tian, Kevin" <kevin.tian@xxxxxxxxx>
Date: Thu, 25 Sep 2008 16:29:27 +0800
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Thread-topic: [Xen-devel] [Patch] x86: enforce strict memory order for x2apic
>From: Jan Beulich [mailto:jbeulich@xxxxxxxxxx]
>Sent: 2008年9月25日 16:25
>>>> "Tian, Kevin" <kevin.tian@xxxxxxxxx> 25.09.08 08:55 >>>
>>We kick a fix by simply using 'mb' instead of 'wmb'.
>>This can effectively enforce program order, as args
>>for WRMSR are loaded from memory. Those memory loads
>>are ordered by mb and so does WRMSR. Alternative is
>The whole change looks a little dubious to me, perhaps largely
>as I can't
>spot which WRMSR (loading its arguments from memory) you're talking

WRMSR to ICR, where EDX/EAX is derived from cpu_online
_map and x86_cpu_to_apicid

>>to add a 'fence' parameter to send_IPI_mask and then
>>only use 'mb' in x2apic version. We think it's not
>>necessary to go with that complexity.
>On the other hand you're penalizing LAPIC systems with this, too. I'm
>not certain that's better than fixing the (incorrect)
>assumptions just in
>the x2APIC case.

I agree. I'll revise the patch to add a 'mb()' in x2APIC instead,
though that may bring a bit overhead to cases when fencing
is not required, like event check IPI.

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