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RE: [Xen-devel] [VTD-NEO][patch 5/6] Intel VT-d/Neocleus 1:1 mregedcode

To: "Muli Ben-Yehuda" <muli@xxxxxxxxxx>
Subject: RE: [Xen-devel] [VTD-NEO][patch 5/6] Intel VT-d/Neocleus 1:1 mregedcode for PCI passthrough
From: "Kay, Allen M" <allen.m.kay@xxxxxxxxx>
Date: Wed, 19 Sep 2007 16:55:11 -0700
Cc: xen-devel@xxxxxxxxxxxxxxxxxxx, Guy Zana <guy@xxxxxxxxxxxx>
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Thread-topic: [Xen-devel] [VTD-NEO][patch 5/6] Intel VT-d/Neocleus 1:1 mregedcode for PCI passthrough
My informal tests did not show much performance degradation. It is not
easy to figure out miss rates without performance counters.

If you look at the latest vt-d spec on the web, there is a passthru
feature in the context entry which will allow passthru DMA on BDF
granularity in the future.



>-----Original Message-----
>From: Muli Ben-Yehuda [mailto:muli@xxxxxxxxxx] 
>Sent: Tuesday, September 18, 2007 11:38 PM
>To: Kay, Allen M
>Cc: Keir Fraser; xen-devel@xxxxxxxxxxxxxxxxxxx; Guy Zana
>Subject: Re: [Xen-devel] [VTD-NEO][patch 5/6] Intel 
>VT-d/Neocleus 1:1 mregedcode for PCI passthrough
>On Tue, Sep 18, 2007 at 11:32:25PM -0700, Kay, Allen M wrote:
>> Translation enabling is on per vt-d engine granularity - not BDF
>> granularity.  Each BDF context entry can point to a different page
>> table structure.
>> Setup a single 1:1 mapping structure to be used by all PV domains is
>> a good idea.  I will give it a try tomorrow.
>I see, thanks for clarifying. That seems pretty strange... do you have
>a notion of the overhead incured by the 1-1 mapping and the average
>IOTLB hit/miss rates?

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