This is an archived copy of the Xen.org mailing list, which we have preserved to ensure that existing links to archives are not broken. The live archive, which contains the latest emails, can be found at http://lists.xen.org/
Home Products Support Community News


RE: [Xen-devel] idle_pg_tables??

To: "PUCCETTI Armand" <armand.puccetti@xxxxxx>
Subject: RE: [Xen-devel] idle_pg_tables??
From: "Petersson, Mats" <Mats.Petersson@xxxxxxx>
Date: Tue, 5 Sep 2006 16:03:02 +0200
Cc: xen-devel@xxxxxxxxxxxxxxxxxxx
Delivery-date: Tue, 05 Sep 2006 07:03:44 -0700
Envelope-to: www-data@xxxxxxxxxxxxxxxxxx
In-reply-to: <44FD5668.7080806@xxxxxx>
List-help: <mailto:xen-devel-request@lists.xensource.com?subject=help>
List-id: Xen developer discussion <xen-devel.lists.xensource.com>
List-post: <mailto:xen-devel@lists.xensource.com>
List-subscribe: <http://lists.xensource.com/cgi-bin/mailman/listinfo/xen-devel>, <mailto:xen-devel-request@lists.xensource.com?subject=subscribe>
List-unsubscribe: <http://lists.xensource.com/cgi-bin/mailman/listinfo/xen-devel>, <mailto:xen-devel-request@lists.xensource.com?subject=unsubscribe>
Sender: xen-devel-bounces@xxxxxxxxxxxxxxxxxxx
Thread-index: AcbQ2Pou0PxxfzMsSd6zBin//90koAACQgOg
Thread-topic: [Xen-devel] idle_pg_tables??
> OK, pages are 2MB in size on AMD64. Now, what is the supposed size of
> that idle_pgtable_l2? According to page.h, the C view of that 
> variable is
> extern l2_pgentry_t   idle_pg_table_l2[ROOT_PAGETABLE_ENTRIES]
> but according to x86_64.S, the memory area where that variable is 
> placed, namely
> between 0x4000 and 0x4000+PAGE_SIZE is much bigger. What is the real 
> size of that
> variable?
> Same question for the idle_pgtable_l4 and _l3? They are, a 
> priori, 512*8 
> bytes=2M long...

Last time I calculated 512 * 8 it came to 4096 (sizeof(l2_pgentry_t)
should be 8 bytes, as we're using PAE-mode in 64-bit code, and thus 8
bytes per page-table-entry). PAGE_SIZE is the basic x86 page-size of
4096, I would assume, so 512 * 8 = PAGE_SIZE, and thus it's NOT much

All page-table entries that point to another page-table entry will point
to an even 4K page, which means, also, that they have 512 entries in
PAE-mode. In non-PAE mode each entry is 4 bytes and there are 1024
entries on each page. It depends on the actual entry in the table
whether it terminates the page-table on L2 or L1. If bit 7 of the L2
entry is set, that means that the entry is a 2MB entry, and thus the
entry is indicated by the bits above bit 20 (or put another way, bits 21
and up will contain the physical address of the memory actually used by
the processor - it is then combined with bits 20 and down from the
location indicated by the code, which is the offset into the memory).
For example:

0x000002bcdef0 as an address. In binary:
47   43   39   35   31   27   23   19   15   11   7    3  (msb number)

CR3 = idle_pg_table = 0x102000
Bits 47..39 -> 0.0000.0000 => 0x1020000 + (0 * 8) => idle_pg_table_l3
Bits 38..30 -> 0.0000.0000 => 0x1030000 + (0 * 8) => idle_pg_table_l2
Bits 29..21 -> 0.0001.0101 => 0x1040000 + (21 * 8) => 1040A8 ->

This means the base addres is 10MB + offset of the lower 21 bits of the
number 1.1100.1101.1110.1111.0000 -> 1CBDEF0, which means that the
address is 2CBDEF0 - which is what we'd expect, as it's a linear


Xen-devel mailing list

<Prev in Thread] Current Thread [Next in Thread>