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Re: [Xen-devel][PATCH]Fix the read error from IRR,ISR and TMR

To: "Dong, Eddie" <eddie.dong@xxxxxxxxx>, "Xin, Xiaohui" <xiaohui.xin@xxxxxxxxx>, <xen-devel@xxxxxxxxxxxxxxxxxxx>
Subject: Re: [Xen-devel][PATCH]Fix the read error from IRR,ISR and TMR
From: Keir Fraser <Keir.Fraser@xxxxxxxxxxxx>
Date: Fri, 01 Sep 2006 15:43:50 +0100
Delivery-date: Fri, 01 Sep 2006 07:44:08 -0700
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Ok, I hadn't considered this. I'll reconsider the patch!

 -- Keir

On 1/9/06 8:44 am, "Dong, Eddie" <eddie.dong@xxxxxxxxx> wrote:

> Yes, skipping the unused parts and compact them together will
> benefit us now :-) While then we may not be able to do CR8 acceleration.
> The later one will need an APIC page to back for guest APIC states,
> currently it is only TPR (CR8) base on VT spec. So 4K memory per
> processor for each APIC page is unavoidable.
> Meanwhile, we are thinking about another important enhancement
> to accelerate some proprietary OS which will frequently access TPR. In
> that patch, the APIC page is directly mapped to guest as "RO" that
> greatly increase UP OS performance in our test. But the patch today is
> still hold on due to SMP support issue, as today's shadow page table is
> still global. I believe eventually shadow page table will be per VP, and
> the APIC acceleration patch will be out too. Then eventually we need to
> organize the APIC data in hardware format like Xiaohui's patch show.

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