===== xen/arch/x86/Rules.mk 1.29 vs edited ===== --- 1.29/xen/arch/x86/Rules.mk 2004-08-10 15:11:59 -06:00 +++ edited/xen/arch/x86/Rules.mk 2004-12-05 20:49:11 -07:00 @@ -12,7 +12,7 @@ CFLAGS += -msoft-float ifeq ($(TARGET_SUBARCH),x86_32) -CFLAGS += -m32 -march=i686 +CFLAGS += -m32 -march=i586 LDFLAGS := --oformat elf32-i386 endif ===== xen/arch/x86/setup.c 1.63 vs edited ===== --- 1.63/xen/arch/x86/setup.c 2004-08-25 09:40:13 -06:00 +++ edited/xen/arch/x86/setup.c 2004-12-05 20:49:11 -07:00 @@ -32,7 +32,7 @@ #if defined(__x86_64__) unsigned long mmu_cr4_features = X86_CR4_PSE | X86_CR4_PGE | X86_CR4_PAE; #else -unsigned long mmu_cr4_features = X86_CR4_PSE | X86_CR4_PGE; +unsigned long mmu_cr4_features = X86_CR4_PGE; #endif EXPORT_SYMBOL(mmu_cr4_features); ===== xen/arch/x86/boot/x86_32.S 1.26 vs edited ===== --- 1.26/xen/arch/x86/boot/x86_32.S 2004-07-14 11:36:28 -06:00 +++ edited/xen/arch/x86/boot/x86_32.S 2004-12-05 20:49:12 -07:00 @@ -79,7 +79,7 @@ /* Set up CR4, except global flag which Intel requires should be */ /* left until after paging is enabled (IA32 Manual Vol. 3, Sec. 2.5) */ mov mmu_cr4_features-__PAGE_OFFSET,%ecx - and $0x7f,%cl # CR4.PGE (global enable) + and $0xf,%cl # CR4.PGE (global enable) mov %ecx,%cr4 cmp $(SECONDARY_CPU_FLAG),%ebx @@ -100,19 +100,29 @@ xor %eax,%eax rep stosb - /* Initialize low and high mappings of all memory with 4MB pages */ - mov $idle_pg_table-__PAGE_OFFSET,%edi - mov $0x1e3,%eax /* PRESENT+RW+A+D+4MB+GLOBAL */ -1: mov %eax,__PAGE_OFFSET>>20(%edi) /* high mapping */ + /* Initialize low and high mappings of all memory */ + /* build Page Table with 4kb pages */ + mov $idle_pg_table_four-__PAGE_OFFSET,%edi + mov $0x23,%eax /* PRESENT+RW+A */ +1: mov %eax,__PAGE_OFFSET>>10(%edi) /* high mapping */ stosl /* low mapping */ - add $(1<>L2_PAGETABLE_SHIFT]) >> PAGE_SHIFT) extern l2_pgentry_t idle_pg_table[ENTRIES_PER_L2_PAGETABLE]; +extern l2_pgentry_t idle_pg_table_four[ENTRIES_PER_L2_PAGETABLE*ENTRIES_PER_L2_PAGETABLE]; extern void paging_init(void); #define __flush_tlb() \