# HG changeset patch
# User Jan Beulich <jbeulich@xxxxxxxxxx>
# Date 1311081291 -3600
# Node ID fd97ca086df6808bffc6ecf3f79cebca64c60bc3
# Parent 4dc6a9ba90d60fdf0cc0898fc9a8fe84ae9030fc
x86: update Intel CPUID masking code to latest spec
..., which adds masking of the xsave feature leaf.
Also add back (and fix to actually make it do what it was supposed to
do from the beginning) the printing of what specific masking couldn't
be done in case the user requested something the hardware doesn't
support.
Signed-off-by: Jan Beulich <jbeulich@xxxxxxxxxx>
---
diff -r 4dc6a9ba90d6 -r fd97ca086df6 xen/arch/x86/cpu/common.c
--- a/xen/arch/x86/cpu/common.c Tue Jul 19 14:14:08 2011 +0100
+++ b/xen/arch/x86/cpu/common.c Tue Jul 19 14:14:51 2011 +0100
@@ -20,10 +20,15 @@
static bool_t __cpuinitdata use_xsave = 1;
boolean_param("xsave", use_xsave);
+
unsigned int __devinitdata opt_cpuid_mask_ecx = ~0u;
integer_param("cpuid_mask_ecx", opt_cpuid_mask_ecx);
unsigned int __devinitdata opt_cpuid_mask_edx = ~0u;
integer_param("cpuid_mask_edx", opt_cpuid_mask_edx);
+
+unsigned int __devinitdata opt_cpuid_mask_xsave_eax = ~0u;
+integer_param("cpuid_mask_xsave_eax", opt_cpuid_mask_xsave_eax);
+
unsigned int __devinitdata opt_cpuid_mask_ext_ecx = ~0u;
integer_param("cpuid_mask_ext_ecx", opt_cpuid_mask_ext_ecx);
unsigned int __devinitdata opt_cpuid_mask_ext_edx = ~0u;
diff -r 4dc6a9ba90d6 -r fd97ca086df6 xen/arch/x86/cpu/cpu.h
--- a/xen/arch/x86/cpu/cpu.h Tue Jul 19 14:14:08 2011 +0100
+++ b/xen/arch/x86/cpu/cpu.h Tue Jul 19 14:14:51 2011 +0100
@@ -22,6 +22,7 @@
extern struct cpu_dev * cpu_devs [X86_VENDOR_NUM];
extern unsigned int opt_cpuid_mask_ecx, opt_cpuid_mask_edx;
+extern unsigned int opt_cpuid_mask_xsave_eax;
extern unsigned int opt_cpuid_mask_ext_ecx, opt_cpuid_mask_ext_edx;
extern int get_model_name(struct cpuinfo_x86 *c);
diff -r 4dc6a9ba90d6 -r fd97ca086df6 xen/arch/x86/cpu/intel.c
--- a/xen/arch/x86/cpu/intel.c Tue Jul 19 14:14:08 2011 +0100
+++ b/xen/arch/x86/cpu/intel.c Tue Jul 19 14:14:51 2011 +0100
@@ -57,6 +57,9 @@
*/
static void __devinit set_cpuidmask(const struct cpuinfo_x86 *c)
{
+ u32 eax, edx;
+ const char *extra = "";
+
if (!~(opt_cpuid_mask_ecx & opt_cpuid_mask_edx &
opt_cpuid_mask_ext_ecx & opt_cpuid_mask_ext_edx))
return;
@@ -71,7 +74,11 @@
wrmsr(MSR_INTEL_CPUID_FEATURE_MASK,
opt_cpuid_mask_ecx,
opt_cpuid_mask_edx);
- if (!~(opt_cpuid_mask_ext_ecx & opt_cpuid_mask_ext_edx))
+ if (~(opt_cpuid_mask_ext_ecx & opt_cpuid_mask_ext_edx))
+ extra = "extended ";
+ else if (~opt_cpuid_mask_xsave_eax)
+ extra = "xsave ";
+ else
return;
break;
/*
@@ -92,11 +99,25 @@
wrmsr(MSR_INTEL_CPUID80000001_FEATURE_MASK,
opt_cpuid_mask_ext_ecx,
opt_cpuid_mask_ext_edx);
+ if (!~opt_cpuid_mask_xsave_eax)
+ return;
+ extra = "xsave ";
+ break;
+ case 0x2a:
+ wrmsr(MSR_INTEL_CPUID1_FEATURE_MASK_V2,
+ opt_cpuid_mask_ecx,
+ opt_cpuid_mask_edx);
+ rdmsr(MSR_INTEL_CPUIDD_01_FEATURE_MASK, eax, edx);
+ wrmsr(MSR_INTEL_CPUIDD_01_FEATURE_MASK,
+ opt_cpuid_mask_xsave_eax, edx);
+ wrmsr(MSR_INTEL_CPUID80000001_FEATURE_MASK_V2,
+ opt_cpuid_mask_ext_ecx,
+ opt_cpuid_mask_ext_edx);
return;
}
- printk(XENLOG_ERR "Cannot set CPU feature mask on CPU#%d\n",
- smp_processor_id());
+ printk(XENLOG_ERR "Cannot set CPU %sfeature mask on CPU#%d\n",
+ extra, smp_processor_id());
}
void __devinit early_intel_workaround(struct cpuinfo_x86 *c)
diff -r 4dc6a9ba90d6 -r fd97ca086df6 xen/include/asm-x86/msr-index.h
--- a/xen/include/asm-x86/msr-index.h Tue Jul 19 14:14:08 2011 +0100
+++ b/xen/include/asm-x86/msr-index.h Tue Jul 19 14:14:51 2011 +0100
@@ -492,6 +492,10 @@
#define MSR_INTEL_CPUID1_FEATURE_MASK 0x00000130
#define MSR_INTEL_CPUID80000001_FEATURE_MASK 0x00000131
+#define MSR_INTEL_CPUID1_FEATURE_MASK_V2 0x00000132
+#define MSR_INTEL_CPUID80000001_FEATURE_MASK_V2 0x00000133
+#define MSR_INTEL_CPUIDD_01_FEATURE_MASK 0x00000134
+
/* Intel cpuid faulting MSRs */
#define MSR_INTEL_PLATFORM_INFO 0x000000ce
#define MSR_INTEL_MISC_FEATURES_ENABLES 0x00000140
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