# HG changeset patch
# User Jan Beulich <jbeulich@xxxxxxxxxx>
# Date 1300468519 0
# Node ID b59e98bc6ff12f0ea436fd1a2defecaaffbfffff
# Parent 5ede16d7c12c03eb96c22f5a5e8780cbbd1282cd
x86/mce: CPU notifiers must not be registered a second time during resume
While c/s 22964:f71212f712fd and 23051:93c864c16ab1 fixed issues with
CPU onlining, they introduced a problem with resume: mcheck_init() is
also being called on that path, and hence checking whether it's
running on CPU 0, which is generally not a really good thing, is
particularly inappropriate here.
Signed-off-by: Jan Beulich <jbeulich@xxxxxxxxxx>
---
diff -r 5ede16d7c12c -r b59e98bc6ff1 xen/arch/x86/acpi/power.c
--- a/xen/arch/x86/acpi/power.c Fri Mar 18 16:31:11 2011 +0000
+++ b/xen/arch/x86/acpi/power.c Fri Mar 18 17:15:19 2011 +0000
@@ -187,7 +187,7 @@
device_power_up();
- mcheck_init(&boot_cpu_data);
+ mcheck_init(&boot_cpu_data, 0);
write_cr4(cr4);
printk(XENLOG_INFO "Finishing wakeup from ACPI S%d state.\n", state);
diff -r 5ede16d7c12c -r b59e98bc6ff1 xen/arch/x86/cpu/common.c
--- a/xen/arch/x86/cpu/common.c Fri Mar 18 16:31:11 2011 +0000
+++ b/xen/arch/x86/cpu/common.c Fri Mar 18 17:15:19 2011 +0000
@@ -431,19 +431,13 @@
/* AND the already accumulated flags with these */
for ( i = 0 ; i < NCAPINTS ; i++ )
boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
+
+ mcheck_init(c, 0);
+ } else {
+ mcheck_init(c, 1);
+
+ mtrr_bp_init();
}
-
- /* Init Machine Check Exception if available. */
- mcheck_init(c);
-
-#if 0
- if (c == &boot_cpu_data)
- sysenter_setup();
- enable_sep_cpu();
-#endif
-
- if (c == &boot_cpu_data)
- mtrr_bp_init();
}
/* cpuid returns the value latched in the HW at reset, not the APIC ID
diff -r 5ede16d7c12c -r b59e98bc6ff1 xen/arch/x86/cpu/mcheck/mce.c
--- a/xen/arch/x86/cpu/mcheck/mce.c Fri Mar 18 16:31:11 2011 +0000
+++ b/xen/arch/x86/cpu/mcheck/mce.c Fri Mar 18 17:15:19 2011 +0000
@@ -793,7 +793,7 @@
};
/* This has to be run for each processor */
-void mcheck_init(struct cpuinfo_x86 *c)
+void mcheck_init(struct cpuinfo_x86 *c, bool_t bsp)
{
enum mcheck_type inited = mcheck_none;
@@ -822,7 +822,7 @@
switch (c->x86) {
case 6:
case 15:
- inited = intel_mcheck_init(c);
+ inited = intel_mcheck_init(c, bsp);
break;
}
break;
@@ -844,7 +844,7 @@
/* Turn on MCE now */
set_in_cr4(X86_CR4_MCE);
- if ( smp_processor_id() == 0 )
+ if ( bsp )
{
/* Early MCE initialisation for BSP. */
if ( cpu_poll_bankmask_alloc(0) )
diff -r 5ede16d7c12c -r b59e98bc6ff1 xen/arch/x86/cpu/mcheck/mce.h
--- a/xen/arch/x86/cpu/mcheck/mce.h Fri Mar 18 16:31:11 2011 +0000
+++ b/xen/arch/x86/cpu/mcheck/mce.h Fri Mar 18 17:15:19 2011 +0000
@@ -42,7 +42,7 @@
enum mcheck_type amd_k8_mcheck_init(struct cpuinfo_x86 *c);
enum mcheck_type amd_f10_mcheck_init(struct cpuinfo_x86 *c);
-enum mcheck_type intel_mcheck_init(struct cpuinfo_x86 *c);
+enum mcheck_type intel_mcheck_init(struct cpuinfo_x86 *c, bool_t bsp);
void intel_mcheck_timer(struct cpuinfo_x86 *c);
void mce_intel_feature_init(struct cpuinfo_x86 *c);
diff -r 5ede16d7c12c -r b59e98bc6ff1 xen/arch/x86/cpu/mcheck/mce_intel.c
--- a/xen/arch/x86/cpu/mcheck/mce_intel.c Fri Mar 18 16:31:11 2011 +0000
+++ b/xen/arch/x86/cpu/mcheck/mce_intel.c Fri Mar 18 17:15:19 2011 +0000
@@ -1297,9 +1297,9 @@
};
/* p4/p6 family have similar MCA initialization process */
-enum mcheck_type intel_mcheck_init(struct cpuinfo_x86 *c)
+enum mcheck_type intel_mcheck_init(struct cpuinfo_x86 *c, bool_t bsp)
{
- if ( smp_processor_id() == 0 )
+ if ( bsp )
{
/* Early MCE initialisation for BSP. */
if ( cpu_mcabank_alloc(0) )
diff -r 5ede16d7c12c -r b59e98bc6ff1 xen/include/asm-x86/processor.h
--- a/xen/include/asm-x86/processor.h Fri Mar 18 16:31:11 2011 +0000
+++ b/xen/include/asm-x86/processor.h Fri Mar 18 17:15:19 2011 +0000
@@ -555,7 +555,7 @@
extern void mtrr_ap_init(void);
extern void mtrr_bp_init(void);
-void mcheck_init(struct cpuinfo_x86 *c);
+void mcheck_init(struct cpuinfo_x86 *c, bool_t bsp);
#define DECLARE_TRAP_HANDLER(_name) \
asmlinkage void _name(void); \
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