# HG changeset patch
# User Keir Fraser <keir@xxxxxxx>
# Date 1296032676 0
# Node ID aadbc956e0d7a4ecf5aff3b683e28abfd4a7f0e7
# Parent 8fa76bc21363d7dbc3fbc7d0333e6668a5953ebe
x86: blacklist new AMD CPUID bits for PV domains
there are some new CPUID bits (and leaves) which Dom0 and PV domains
should not see to avoid trouble, since we don't emulate the features.
The most prominent one is a topology leaf, which contains information
specific to the physical CPU, not the virtual one. To avoid confusion
(and possibly crashes) due to a confused Dom0 scheduler simply disable
these bits.
Signed-off-by: Andre Przywara <andre.przywara@xxxxxxx>
Signed-off-by: Keir Fraser <keir@xxxxxxx>
xen-unstable changeset: 22815:4785c70c2b6d
xen-unstable date: Wed Jan 26 08:45:40 2011 +0000
---
tools/libxc/xc_cpufeature.h | 5 +++++
tools/libxc/xc_cpuid_x86.c | 5 +++++
xen/arch/x86/traps.c | 5 +++++
xen/include/asm-x86/cpufeature.h | 5 +++++
4 files changed, 20 insertions(+)
diff -r 8fa76bc21363 -r aadbc956e0d7 tools/libxc/xc_cpufeature.h
--- a/tools/libxc/xc_cpufeature.h Wed Jan 26 09:01:17 2011 +0000
+++ b/tools/libxc/xc_cpufeature.h Wed Jan 26 09:04:36 2011 +0000
@@ -114,5 +114,10 @@
#define X86_FEATURE_SSE5 (6*32+ 11) /* AMD Streaming SIMD Extensions-5 */
#define X86_FEATURE_SKINIT (6*32+ 12) /* SKINIT, STGI/CLGI, DEV */
#define X86_FEATURE_WDT (6*32+ 13) /* Watchdog Timer */
+#define X86_FEATURE_LWP (6*32+15) /* Light Weight Profiling */
+#define X86_FEATURE_FMA4 (6*32+16) /* 4 operands MAC instructions */
+#define X86_FEATURE_NODEID_MSR (6*32+19) /* NodeId MSR */
+#define X86_FEATURE_TBM (6*32+21) /* trailing bit manipulations */
+#define X86_FEATURE_TOPOEXT (6*32+22) /* topology extensions CPUID leafs */
#endif /* __LIBXC_CPUFEATURE_H */
diff -r 8fa76bc21363 -r aadbc956e0d7 tools/libxc/xc_cpuid_x86.c
--- a/tools/libxc/xc_cpuid_x86.c Wed Jan 26 09:01:17 2011 +0000
+++ b/tools/libxc/xc_cpuid_x86.c Wed Jan 26 09:04:36 2011 +0000
@@ -341,11 +341,16 @@ static void xc_cpuid_pv_policy(
clear_bit(X86_FEATURE_IBS, regs[2]);
clear_bit(X86_FEATURE_SKINIT, regs[2]);
clear_bit(X86_FEATURE_WDT, regs[2]);
+ clear_bit(X86_FEATURE_LWP, regs[2]);
+ clear_bit(X86_FEATURE_NODEID_MSR, regs[2]);
+ clear_bit(X86_FEATURE_TOPOEXT, regs[2]);
break;
case 5: /* MONITOR/MWAIT */
case 0xa: /* Architectural Performance Monitor Features */
case 0x8000000a: /* SVM revision and features */
case 0x8000001b: /* Instruction Based Sampling */
+ case 0x8000001c: /* Light Weight Profiling */
+ case 0x8000001e: /* Extended topology reporting */
regs[0] = regs[1] = regs[2] = regs[3] = 0;
break;
}
diff -r 8fa76bc21363 -r aadbc956e0d7 xen/arch/x86/traps.c
--- a/xen/arch/x86/traps.c Wed Jan 26 09:01:17 2011 +0000
+++ b/xen/arch/x86/traps.c Wed Jan 26 09:04:36 2011 +0000
@@ -813,11 +813,16 @@ static void pv_cpuid(struct cpu_user_reg
__clear_bit(X86_FEATURE_IBS % 32, &c);
__clear_bit(X86_FEATURE_SKINIT % 32, &c);
__clear_bit(X86_FEATURE_WDT % 32, &c);
+ __clear_bit(X86_FEATURE_LWP % 32, &c);
+ __clear_bit(X86_FEATURE_NODEID_MSR % 32, &c);
+ __clear_bit(X86_FEATURE_TOPOEXT % 32, &c);
break;
case 5: /* MONITOR/MWAIT */
case 0xa: /* Architectural Performance Monitor Features */
case 0x8000000a: /* SVM revision and features */
case 0x8000001b: /* Instruction Based Sampling */
+ case 0x8000001c: /* Light Weight Profiling */
+ case 0x8000001e: /* Extended topology reporting */
a = b = c = d = 0;
break;
default:
diff -r 8fa76bc21363 -r aadbc956e0d7 xen/include/asm-x86/cpufeature.h
--- a/xen/include/asm-x86/cpufeature.h Wed Jan 26 09:01:17 2011 +0000
+++ b/xen/include/asm-x86/cpufeature.h Wed Jan 26 09:04:36 2011 +0000
@@ -129,6 +129,11 @@
#define X86_FEATURE_SSE5 (6*32+ 11) /* AMD Streaming SIMD Extensions-5 */
#define X86_FEATURE_SKINIT (6*32+ 12) /* SKINIT, STGI/CLGI, DEV */
#define X86_FEATURE_WDT (6*32+ 13) /* Watchdog Timer */
+#define X86_FEATURE_LWP (6*32+15) /* Light Weight Profiling */
+#define X86_FEATURE_FMA4 (6*32+16) /* 4 operands MAC instructions */
+#define X86_FEATURE_NODEID_MSR (6*32+19) /* NodeId MSR */
+#define X86_FEATURE_TBM (6*32+21) /* trailing bit manipulations */
+#define X86_FEATURE_TOPOEXT (6*32+22) /* topology extensions CPUID leafs */
#define cpu_has(c, bit) test_bit(bit, (c)->x86_capability)
#define boot_cpu_has(bit) test_bit(bit, boot_cpu_data.x86_capability)
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