# HG changeset patch
# User Keir Fraser <keir.fraser@xxxxxxxxxx>
# Date 1262955982 0
# Node ID b8c2a9aacba6d9c50847d419bc6cfedc8fc4c750
# Parent 0b5ca7cdbdfc8857229475519b23a78401829e91
Update Solarflare Communications resource driver to version 3.0.2.2074
to match net driver update.
Add support for new SFC9000 series NICs
Signed-off-by: Kieran Mansley <kmansley@xxxxxxxxxxxxxx>
---
drivers/net/sfc/sfc_resource/ci/driver/efab/hardware/falcon/falcon_core.h
| 1149 --
drivers/net/sfc/sfc_resource/ci/driver/efab/hardware/workarounds.h
| 75
drivers/net/sfc/sfc_resource/falcon_mac.c
| 171
drivers/net/sfc/sfc_resource/Makefile
| 2
drivers/net/sfc/sfc_resource/assert_valid.c
| 15
drivers/net/sfc/sfc_resource/buddy.c
| 95
drivers/net/sfc/sfc_resource/buffer_table.c
| 47
drivers/net/sfc/sfc_resource/ci/driver/efab/hardware.h
| 110
drivers/net/sfc/sfc_resource/ci/driver/efab/hardware/common.h
| 8
drivers/net/sfc/sfc_resource/ci/driver/efab/hardware/falcon.h
| 119
drivers/net/sfc/sfc_resource/ci/driver/efab/hardware/falcon/falcon_desc.h
| 2
drivers/net/sfc/sfc_resource/ci/driver/efab/hardware/falcon/falcon_event.h
| 4
drivers/net/sfc/sfc_resource/ci/driver/efab/hardware/falcon/falcon_grmon.h
| 2
drivers/net/sfc/sfc_resource/ci/driver/efab/hardware/falcon/falcon_intr_vec.h
| 2
drivers/net/sfc/sfc_resource/ci/driver/efab/hardware/falcon/falcon_mac.h
| 4
drivers/net/sfc/sfc_resource/ci/driver/efab/hardware/falcon/falcon_xgrmon.h
| 2
drivers/net/sfc/sfc_resource/ci/driver/efab/hardware/host_common.h
| 2850 +++++++
drivers/net/sfc/sfc_resource/ci/driver/efab/hardware/host_common_mac.h
| 730 +
drivers/net/sfc/sfc_resource/ci/driver/efab/hardware/host_common_pci_defs.h
| 2057 +++++
drivers/net/sfc/sfc_resource/ci/driver/resource/efx_vi.h
| 6
drivers/net/sfc/sfc_resource/ci/driver/resource/linux_efhw_nic.h
| 16
drivers/net/sfc/sfc_resource/ci/efhw/checks.h
| 97
drivers/net/sfc/sfc_resource/ci/efhw/common.h
| 51
drivers/net/sfc/sfc_resource/ci/efhw/common_sysdep.h
| 12
drivers/net/sfc/sfc_resource/ci/efhw/debug.h
| 10
drivers/net/sfc/sfc_resource/ci/efhw/efhw_config.h
| 2
drivers/net/sfc/sfc_resource/ci/efhw/efhw_types.h
| 155
drivers/net/sfc/sfc_resource/ci/efhw/eventq.h
| 4
drivers/net/sfc/sfc_resource/ci/efhw/eventq_macros.h
| 12
drivers/net/sfc/sfc_resource/ci/efhw/falcon.h
| 17
drivers/net/sfc/sfc_resource/ci/efhw/falcon_hash.h
| 30
drivers/net/sfc/sfc_resource/ci/efhw/hardware_sysdep.h
| 7
drivers/net/sfc/sfc_resource/ci/efhw/iopage.h
| 2
drivers/net/sfc/sfc_resource/ci/efhw/iopage_types.h
| 2
drivers/net/sfc/sfc_resource/ci/efhw/nic.h
| 2
drivers/net/sfc/sfc_resource/ci/efhw/public.h
| 41
drivers/net/sfc/sfc_resource/ci/efhw/sysdep.h
| 17
drivers/net/sfc/sfc_resource/ci/efrm/buddy.h
| 5
drivers/net/sfc/sfc_resource/ci/efrm/buffer_table.h
| 17
drivers/net/sfc/sfc_resource/ci/efrm/debug.h
| 4
drivers/net/sfc/sfc_resource/ci/efrm/driver_private.h
| 13
drivers/net/sfc/sfc_resource/ci/efrm/efrm_client.h
| 65
drivers/net/sfc/sfc_resource/ci/efrm/efrm_nic.h
| 58
drivers/net/sfc/sfc_resource/ci/efrm/filter.h
| 101
drivers/net/sfc/sfc_resource/ci/efrm/iobufset.h
| 37
drivers/net/sfc/sfc_resource/ci/efrm/nic_set.h
| 2
drivers/net/sfc/sfc_resource/ci/efrm/nic_table.h
| 4
drivers/net/sfc/sfc_resource/ci/efrm/private.h
| 35
drivers/net/sfc/sfc_resource/ci/efrm/resource.h
| 23
drivers/net/sfc/sfc_resource/ci/efrm/resource_id.h
| 6
drivers/net/sfc/sfc_resource/ci/efrm/sysdep.h
| 6
drivers/net/sfc/sfc_resource/ci/efrm/sysdep_linux.h
| 14
drivers/net/sfc/sfc_resource/ci/efrm/vi_resource.h
| 54
drivers/net/sfc/sfc_resource/ci/efrm/vi_resource_manager.h
| 59
drivers/net/sfc/sfc_resource/ci/efrm/vi_resource_private.h
| 25
drivers/net/sfc/sfc_resource/driver_object.c
| 212
drivers/net/sfc/sfc_resource/driverlink_new.c
| 75
drivers/net/sfc/sfc_resource/efrm_internal.h
| 73
drivers/net/sfc/sfc_resource/efx_vi_shm.c
| 129
drivers/net/sfc/sfc_resource/eventq.c
| 40
drivers/net/sfc/sfc_resource/falcon.c
| 3855 +++++-----
drivers/net/sfc/sfc_resource/falcon_hash.c
| 223
drivers/net/sfc/sfc_resource/filter_resource.c
| 285
drivers/net/sfc/sfc_resource/iobufset_resource.c
| 167
drivers/net/sfc/sfc_resource/iopage.c
| 16
drivers/net/sfc/sfc_resource/kernel_compat.c
| 26
drivers/net/sfc/sfc_resource/kernel_compat.h
| 30
drivers/net/sfc/sfc_resource/kernel_proc.c
| 10
drivers/net/sfc/sfc_resource/kfifo.c
| 16
drivers/net/sfc/sfc_resource/linux_resource_internal.h
| 14
drivers/net/sfc/sfc_resource/nic.c
| 59
drivers/net/sfc/sfc_resource/resource_driver.c
| 158
drivers/net/sfc/sfc_resource/resource_manager.c
| 222
drivers/net/sfc/sfc_resource/resources.c
| 2
drivers/net/sfc/sfc_resource/vi_resource_alloc.c
| 226
drivers/net/sfc/sfc_resource/vi_resource_event.c
| 132
drivers/net/sfc/sfc_resource/vi_resource_flush.c
| 320
drivers/net/sfc/sfc_resource/vi_resource_manager.c
| 52
78 files changed, 9696 insertions(+), 5101 deletions(-)
diff -r 0b5ca7cdbdfc -r b8c2a9aacba6 drivers/net/sfc/sfc_resource/Makefile
--- a/drivers/net/sfc/sfc_resource/Makefile Fri Jan 08 13:05:49 2010 +0000
+++ b/drivers/net/sfc/sfc_resource/Makefile Fri Jan 08 13:06:22 2010 +0000
@@ -7,7 +7,7 @@ EXTRA_CFLAGS += -Idrivers/net/sfc -Idriv
sfc_resource-objs := resource_driver.o iopage.o efx_vi_shm.o \
driverlink_new.o kernel_proc.o kfifo.o \
- nic.o eventq.o falcon.o falcon_mac.o falcon_hash.o \
+ nic.o eventq.o falcon.o falcon_hash.o \
assert_valid.o buddy.o buffer_table.o filter_resource.o \
iobufset_resource.o resource_manager.o resources.o \
vi_resource_alloc.o vi_resource_event.o vi_resource_flush.o \
diff -r 0b5ca7cdbdfc -r b8c2a9aacba6 drivers/net/sfc/sfc_resource/assert_valid.c
--- a/drivers/net/sfc/sfc_resource/assert_valid.c Fri Jan 08 13:05:49
2010 +0000
+++ b/drivers/net/sfc/sfc_resource/assert_valid.c Fri Jan 08 13:06:22
2010 +0000
@@ -6,7 +6,7 @@
* This file contains functions to assert validness of resources and
* resource manager in DEBUG build of the resource driver.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
@@ -50,8 +50,6 @@ efrm_resource_manager_assert_valid(struc
_EFRM_ASSERT(rm, file, line);
_EFRM_ASSERT(rm->rm_name, file, line);
_EFRM_ASSERT(rm->rm_type < EFRM_RESOURCE_NUM, file, line);
- _EFRM_ASSERT(rm->rm_table, file, line);
- _EFRM_ASSERT(rm->rm_table_size > 0, file, line);
_EFRM_ASSERT(rm->rm_dtor, file, line);
}
EXPORT_SYMBOL(efrm_resource_manager_assert_valid);
@@ -72,19 +70,18 @@ efrm_resource_assert_valid(struct efrm_r
_EFRM_ASSERT(rs, file, line);
if (ref_count_is_zero >= 0) {
- if (!(ref_count_is_zero || atomic_read(&rs->rs_ref_count) > 0)
- || !(!ref_count_is_zero
- || atomic_read(&rs->rs_ref_count) == 0))
+ if (!(ref_count_is_zero || rs->rs_ref_count > 0)
+ || !(!ref_count_is_zero || rs->rs_ref_count == 0))
EFRM_WARN("%s: check %szero ref=%d " EFRM_RESOURCE_FMT,
__FUNCTION__,
ref_count_is_zero == 0 ? "non-" : "",
- atomic_read(&rs->rs_ref_count),
+ rs->rs_ref_count,
EFRM_RESOURCE_PRI_ARG(rs->rs_handle));
_EFRM_ASSERT(!(ref_count_is_zero == 0) ||
- atomic_read(&rs->rs_ref_count) != 0, file, line);
+ rs->rs_ref_count != 0, file, line);
_EFRM_ASSERT(!(ref_count_is_zero > 0) ||
- atomic_read(&rs->rs_ref_count) == 0, file, line);
+ rs->rs_ref_count == 0, file, line);
}
rm = efrm_rm_table[EFRM_RESOURCE_TYPE(rs->rs_handle)];
diff -r 0b5ca7cdbdfc -r b8c2a9aacba6 drivers/net/sfc/sfc_resource/buddy.c
--- a/drivers/net/sfc/sfc_resource/buddy.c Fri Jan 08 13:05:49 2010 +0000
+++ b/drivers/net/sfc/sfc_resource/buddy.c Fri Jan 08 13:06:22 2010 +0000
@@ -1,3 +1,4 @@
+
/****************************************************************************
* Driver for Solarflare network controllers -
* resource management for Xen backend, OpenOnload, etc
@@ -5,7 +6,7 @@
*
* This file contains implementation of a buddy allocator.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
@@ -71,7 +72,7 @@ efrm_buddy_free_list_add(struct efrm_bud
unsigned order, unsigned addr)
{
list_add(&b->links[addr], &b->free_lists[order]);
- b->orders[addr] = (uint8_t) b->order;
+ b->orders[addr] = (uint8_t) order;
}
static inline void
efrm_buddy_free_list_del(struct efrm_buddy_allocator *b, unsigned addr)
@@ -207,7 +208,7 @@ efrm_buddy_free(struct efrm_buddy_alloca
if (!efrm_buddy_addr_in_free_list(b, buddy_addr) ||
b->orders[buddy_addr] != order)
break;
- efrm_buddy_free_list_del(b, addr);
+ efrm_buddy_free_list_del(b, buddy_addr);
if (buddy_addr < addr)
addr = buddy_addr;
++order;
@@ -217,91 +218,3 @@ efrm_buddy_free(struct efrm_buddy_alloca
("buddy - free %x merged into order %d", addr, order););
efrm_buddy_free_list_add(b, order, addr);
}
-
-void efrm_buddy_reserve_at_start(struct efrm_buddy_allocator *b, unsigned n)
-{
- int addr;
- unsigned o;
- EFRM_DO_DEBUG(int n_save = n);
-
- DEBUG_ALLOC(EFRM_NOTICE("%s(%u)", __FUNCTION__, n));
- EFRM_ASSERT(b);
- EFRM_ASSERT(n <= 1u << b->order && n > 0);
- /* Whole space must be free. */
- EFRM_ASSERT(!efrm_buddy_free_list_empty(b, b->order));
-
- o = fls(n);
-
- while (n) {
- while (((unsigned)1 << o) > n)
- --o;
- EFRM_ASSERT(((unsigned)1 << o) <= n);
- addr = efrm_buddy_alloc(b, o);
- EFRM_ASSERT(addr + (1 << o) <= n_save);
- n -= 1 << o;
- }
-}
-
-static int
-__efrm_buddy_reserve_at_end(struct efrm_buddy_allocator *b, unsigned order,
- int threshold)
-{
- unsigned o, addr;
-
- DEBUG_ALLOC(EFRM_NOTICE("%s(%u, %d)", __FUNCTION__, order, threshold));
- EFRM_ASSERT(b);
-
- /* Find largest block; there must be one big enough (or caller has
- ** goofed).
- */
- for (o = b->order;; --o) {
- if (efrm_buddy_free_list_empty(b, o))
- continue;
- addr = efrm_buddy_free_list_first(b, o);
- if (addr + (1 << o) <= (unsigned)threshold)
- continue;
- break;
- }
- EFRM_ASSERT(o >= order);
-
- /* Split down (keeping second half) until we reach
- * the requested size. */
- addr = efrm_buddy_free_list_pop(b, o);
-
- while (o-- > order) {
- efrm_buddy_free_list_add(b, o, addr);
- addr += 1 << o;
- }
-
- EFRM_DO_DEBUG(b->orders[addr] = (uint8_t) order);
-
- return addr;
-}
-
-void efrm_buddy_reserve_at_end(struct efrm_buddy_allocator *b, unsigned n)
-{
- int addr, threshold;
- unsigned o;
- EFRM_DO_DEBUG(int n_save = n);
-
- DEBUG_ALLOC(EFRM_NOTICE("%s(%u)", __FUNCTION__, n));
- DEBUG_ALLOC(efrm_buddy_dump(b));
- EFRM_ASSERT(b);
- EFRM_ASSERT(n <= 1u << b->order);
-
- if (!n)
- return;
-
- threshold = (1 << b->order) - n;
- o = fls(n);
-
- while (n) {
- while (((unsigned)1 << o) > n)
- --o;
- EFRM_ASSERT(((unsigned)1 << o) <= n);
- addr = __efrm_buddy_reserve_at_end(b, o, threshold);
- EFRM_ASSERT(addr >= (1 << b->order) - n_save);
- n -= 1 << o;
- }
- DEBUG_ALLOC(efrm_buddy_dump(b));
-}
diff -r 0b5ca7cdbdfc -r b8c2a9aacba6 drivers/net/sfc/sfc_resource/buffer_table.c
--- a/drivers/net/sfc/sfc_resource/buffer_table.c Fri Jan 08 13:05:49
2010 +0000
+++ b/drivers/net/sfc/sfc_resource/buffer_table.c Fri Jan 08 13:06:22
2010 +0000
@@ -5,7 +5,7 @@
*
* This file contains abstraction of the buffer table on the NIC.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
@@ -51,13 +51,13 @@ static struct efrm_buffer_table efrm_buf
int efrm_buffer_table_ctor(unsigned low, unsigned high)
{
- int log2_n_entries, rc;
+ int log2_n_entries, rc, i;
EFRM_ASSERT(high > 0);
EFRM_ASSERT(low < high);
- EFRM_TRACE("efrm_buffer_table_ctor: low=%u high=%u", low, high);
- EFRM_NOTICE("efrm_buffer_table_ctor: low=%u high=%u", low, high);
+ EFRM_TRACE("%s: low=%u high=%u", __FUNCTION__, low, high);
+ EFRM_NOTICE("%s: low=%u high=%u", __FUNCTION__, low, high);
log2_n_entries = fls(high - 1);
@@ -67,14 +67,17 @@ int efrm_buffer_table_ctor(unsigned low,
"failed (%d)", log2_n_entries, rc);
return rc;
}
+ for (i = 0; i < (1 << log2_n_entries); ++i) {
+ rc = efrm_buddy_alloc(&efrm_buffers.buddy, 0);
+ EFRM_ASSERT(rc >= 0);
+ EFRM_ASSERT(rc < (1 << log2_n_entries));
+ }
+ for (i = low; i < (int) high; ++i)
+ efrm_buddy_free(&efrm_buffers.buddy, i, 0);
spin_lock_init(&efrm_buffers.lock);
- efrm_buddy_reserve_at_start(&efrm_buffers.buddy, low);
- efrm_buddy_reserve_at_end(&efrm_buffers.buddy,
- (1 << log2_n_entries) - high);
-
- EFRM_TRACE("efrm_buffer_table_ctor: done");
+ EFRM_TRACE("%s: done", __FUNCTION__);
return 0;
}
@@ -86,7 +89,7 @@ void efrm_buffer_table_dtor(void)
spin_lock_destroy(&efrm_buffers.lock);
efrm_buddy_dtor(&efrm_buffers.buddy);
- EFRM_TRACE("efrm_buffer_table_dtor: done");
+ EFRM_TRACE("%s: done", __FUNCTION__);
}
/**********************************************************************/
@@ -151,22 +154,18 @@ void efrm_buffer_table_free(struct efhw_
void
efrm_buffer_table_set(struct efhw_buffer_table_allocation *a,
+ struct efhw_nic *nic,
unsigned i, dma_addr_t dma_addr, int owner)
{
- struct efhw_nic *nic;
- int nic_i;
-
EFRM_ASSERT(a);
EFRM_ASSERT(i < (unsigned)1 << a->order);
- EFRM_FOR_EACH_NIC(nic_i, nic)
- efhw_nic_buffer_table_set(nic, dma_addr, EFHW_NIC_PAGE_SIZE,
- 0, owner, a->base + i);
- /* NB. No commit Caller should call efrm_buffer_table_commit. There
- are underlying hardware constraints regarding the number of
- buffer table entries which can be pushed before commiting. */
-}
-
-unsigned long efrm_buffer_table_size(void)
+
+ efhw_nic_buffer_table_set(nic, dma_addr, EFHW_NIC_PAGE_SIZE,
+ 0, owner, a->base + i);
+}
+
+
+int efrm_buffer_table_size(void)
{
return efrm_buddy_size(&efrm_buffers.buddy);
}
@@ -174,7 +173,7 @@ unsigned long efrm_buffer_table_size(voi
/**********************************************************************/
int
-efrm_page_register(dma_addr_t dma_addr, int owner,
+efrm_page_register(struct efhw_nic *nic, dma_addr_t dma_addr, int owner,
efhw_buffer_addr_t *buf_addr_out)
{
struct efhw_buffer_table_allocation alloc;
@@ -182,7 +181,7 @@ efrm_page_register(dma_addr_t dma_addr,
rc = efrm_buffer_table_alloc(0, &alloc);
if (rc == 0) {
- efrm_buffer_table_set(&alloc, 0, dma_addr, owner);
+ efrm_buffer_table_set(&alloc, nic, 0, dma_addr, owner);
efrm_buffer_table_commit();
*buf_addr_out = EFHW_BUFFER_ADDR(alloc.base, 0);
}
diff -r 0b5ca7cdbdfc -r b8c2a9aacba6
drivers/net/sfc/sfc_resource/ci/driver/efab/hardware.h
--- a/drivers/net/sfc/sfc_resource/ci/driver/efab/hardware.h Fri Jan 08
13:05:49 2010 +0000
+++ b/drivers/net/sfc/sfc_resource/ci/driver/efab/hardware.h Fri Jan 08
13:06:22 2010 +0000
@@ -5,7 +5,7 @@
*
* This file provides EtherFabric NIC hardware interface.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
@@ -34,11 +34,11 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
****************************************************************************
*/
-
-#ifndef __CI_DRIVER_EFAB_HARDWARE_H__
+#ifdef __CI_DRIVER_EFAB_HARDWARE_H__
+# error This header should only be included directly in .c files
+#endif
#define __CI_DRIVER_EFAB_HARDWARE_H__
-#include "ci/driver/efab/hardware/workarounds.h"
#include <ci/efhw/hardware_sysdep.h>
@@ -58,7 +58,62 @@
*
*---------------------------------------------------------------------------*/
+#ifdef USE_OLD_HWDEFS
+#define FR_AA_TIMER_COMMAND_REG_KER_OFST 0x00000420
+#define FR_BZ_TIMER_COMMAND_REGP0_OFST 0x00000420
+#define FR_AB_TIMER_COMMAND_REGP123_OFST 0x01000420
+#define FR_AA_TIMER_COMMAND_REGP0_OFST 0x00008420
+#define FR_AA_TX_DESC_UPD_REG_KER_OFST 0x00000a10
+#define FR_AB_TX_DESC_UPD_REGP123_OFST 0x01000a10
+#define FR_AA_TX_DESC_UPD_REGP0_OFST 0x00008a10
+#define FR_AA_RX_DESC_UPD_REG_KER_OFST 0x00000830
+#define FR_AA_RX_DESC_UPD_REGP0_OFST 0x00008830
+#define FR_AB_RX_DESC_UPD_REGP123_OFST 0x01000830
+#else
+#include "ci/driver/efab/hardware/host_common.h"
+#include "ci/driver/efab/hardware/host_common_pci_defs.h"
+#include "ci/driver/efab/hardware/host_common_mac.h"
+
+#define FR_AA_TX_PACE_TBL_FIRST_QUEUE 4
+#define FR_BZ_TX_PACE_TBL_FIRST_QUEUE 0
+
+#define GEN_MODE_REG_KER 0xC90 /* here in B0 too, but not in headers? */
+ #define DATAPATH_LOOPBACK_EN_SIENA_LBN 4
+ #define DATAPATH_LOOPBACK_EN_SIENA_WIDTH 1
+
+#define SIENA_USER_EV_DECODE 8
+#define SIENA_EVENT_CODE_USER ((uint64_t)SIENA_USER_EV_DECODE << EV_CODE_LBN)
+
+#define SIENA_USER_EV_QID_LBN 32
+#define SIENA_USER_EV_QID_WIDTH 10
+#define SIENA_USER_EV_REG_VALUE_LBN 0
+#define SIENA_USER_EV_REG_VALUE_WIDTH 32
+
+#define SIENA_EVENT_USER_QID_MASK \
+ (__FALCON_OPEN_MASK(SIENA_USER_EV_QID_WIDTH) << SIENA_USER_EV_QID_LBN)
+#define SIENA_EVENT_USER_EV_REG_VALUE_MASK \
+ (__FALCON_OPEN_MASK(SIENA_USER_EV_REG_VALUE_WIDTH) << \
+ SIENA_USER_EV_REG_VALUE_LBN)
+
+#define SIENA_EVENT_USER_Q_ID(evp) \
+ (((evp)->u64 & SIENA_EVENT_USER_QID_MASK) >> \
+ SIENA_USER_EV_QID_LBN)
+
+#define SIENA_EVENT_USER_EV_REG_VALUE(evp) \
+ (((evp)->u64 & SIENA_EVENT_USER_EV_REG_VALUE_MASK) >> \
+ SIENA_USER_EV_REG_VALUE_LBN)
+
+/* Additional constants relevant to Siena only */
+
+#define SIENA_RX_PKT_NOT_PARSED_CUTOFF 2560
+#define SIENA_PORT1_MCPUIND_MAP_OFFSET 0x800000
+
+#endif
#include <ci/driver/efab/hardware/falcon.h>
+
+#ifndef __KERNEL__
+#include <ci/driver/efab/hardware/falcon_ul.h>
+#endif
/*----------------------------------------------------------------------------
*
@@ -85,20 +140,20 @@
#define efhw_nic_interrupt_disable(nic) \
((nic)->efhw_func->interrupt_disable(nic))
-#define efhw_nic_set_interrupt_moderation(nic, val) \
- ((nic)->efhw_func->set_interrupt_moderation(nic, val))
+#define efhw_nic_set_interrupt_moderation(nic, evq, val) \
+ ((nic)->efhw_func->set_interrupt_moderation(nic, evq, val))
/*-------------- Event support ------------ */
-#define efhw_nic_event_queue_enable(nic, evq, size, q_base, buf_base) \
- ((nic)->efhw_func->event_queue_enable(nic, evq, size, q_base, \
- buf_base))
+#define efhw_nic_event_queue_enable(nic, evq, size, buf_base, interrupting,
dos_p) \
+ ((nic)->efhw_func->event_queue_enable((nic), (evq), (size), \
+ (buf_base), (interrupting),
(dos_p)))
#define efhw_nic_event_queue_disable(nic, evq, timer_only) \
((nic)->efhw_func->event_queue_disable(nic, evq, timer_only))
-#define efhw_nic_wakeup_request(nic, q_base, index, evq) \
- ((nic)->efhw_func->wakeup_request(nic, q_base, index, evq))
+#define efhw_nic_wakeup_request(nic, rd_ptr, evq) \
+ ((nic)->efhw_func->wakeup_request((nic), (rd_ptr), (evq)))
#define efhw_nic_sw_event(nic, data, ev) \
((nic)->efhw_func->sw_event(nic, data, ev))
@@ -109,14 +164,11 @@
((nic)->efhw_func->ipfilter_set(nic, type, index, dmaq, \
saddr, sport, daddr, dport))
-#define efhw_nic_ipfilter_attach(nic, index, dmaq) \
- ((nic)->efhw_func->ipfilter_attach(nic, index, dmaq))
-
-#define efhw_nic_ipfilter_detach(nic, index) \
- ((nic)->efhw_func->ipfilter_detach(nic, index))
-
#define efhw_nic_ipfilter_clear(nic, index) \
((nic)->efhw_func->ipfilter_clear(nic, index))
+
+#define efhw_nic_ipfilter_redirect(nic, filter_i, rxq_i) \
+ ((nic)->efhw_func->ipfilter_redirect((nic), (filter_i), (rxq_i)))
/*-------------- DMA support ------------ */
#define efhw_nic_dmaq_tx_q_init(nic, dmaq, evq, owner, tag, \
@@ -162,6 +214,14 @@
#define efhw_nic_buffer_table_commit(nic) \
((nic)->efhw_func->buffer_table_commit(nic))
+/*-------------- New filter API ------------ */
+#define efhw_nic_filter_set(nic, spec, index_out) \
+ ((nic)->efhw_func->filter_set(nic, spec, index_out))
+
+#define efhw_nic_filter_clear(nic, type, index_out) \
+ ((nic)->efhw_func->filter_clear(nic, type, index_out))
+
+
/*----------------------------------------------------------------------------
* Hardware specific portability macros for performance critical code.
*
@@ -170,31 +230,15 @@
* marked appropriately
*
*---------------------------------------------------------------------------*/
-
-#if defined(__CI_HARDWARE_CONFIG_FALCON__)
-
-/* --- DMA --- */
-#define EFHW_DMA_ADDRMASK (0xffffffffffffffffULL)
/* --- Buffers --- */
#define EFHW_BUFFER_ADDR FALCON_BUFFER_4K_ADDR
#define EFHW_BUFFER_PAGE FALCON_BUFFER_4K_PAGE
#define EFHW_BUFFER_OFF FALCON_BUFFER_4K_OFF
-/* --- Filters --- */
-#define EFHW_IP_FILTER_NUM FALCON_FILTER_TBL_NUM
-
-#define EFHW_MAX_PAGE_SIZE FALCON_MAX_PAGE_SIZE
-
-#else
-# error no hardware definition found
-#endif
-
#if PAGE_SIZE <= EFHW_MAX_PAGE_SIZE
#define EFHW_NIC_PAGE_SIZE PAGE_SIZE
#else
#define EFHW_NIC_PAGE_SIZE EFHW_MAX_PAGE_SIZE
#endif
#define EFHW_NIC_PAGE_MASK (~(EFHW_NIC_PAGE_SIZE-1))
-
-#endif /* __CI_DRIVER_EFAB_HARDWARE_H__ */
diff -r 0b5ca7cdbdfc -r b8c2a9aacba6
drivers/net/sfc/sfc_resource/ci/driver/efab/hardware/common.h
--- a/drivers/net/sfc/sfc_resource/ci/driver/efab/hardware/common.h Fri Jan
08 13:05:49 2010 +0000
+++ b/drivers/net/sfc/sfc_resource/ci/driver/efab/hardware/common.h Fri Jan
08 13:06:22 2010 +0000
@@ -6,7 +6,7 @@
* This file provides EtherFabric NIC hardware interface common
* definitions.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
@@ -65,4 +65,10 @@
#define EFHW_4G 0x100000000ULL
#define EFHW_8G 0x200000000ULL
+/* --- DMA --- */
+#define EFHW_DMA_ADDRMASK (0xffffffffffffffffULL)
+
+#define EFHW_IP_FILTER_NUM 8192
+#define EFHW_MAX_PAGE_SIZE (EFHW_8K)
+
#endif /* __CI_DRIVER_EFAB_HARDWARE_COMMON_H__ */
diff -r 0b5ca7cdbdfc -r b8c2a9aacba6
drivers/net/sfc/sfc_resource/ci/driver/efab/hardware/falcon.h
--- a/drivers/net/sfc/sfc_resource/ci/driver/efab/hardware/falcon.h Fri Jan
08 13:05:49 2010 +0000
+++ b/drivers/net/sfc/sfc_resource/ci/driver/efab/hardware/falcon.h Fri Jan
08 13:06:22 2010 +0000
@@ -6,7 +6,7 @@
* This file provides EtherFabric NIC - EFXXXX (aka Falcon) specific
* definitions.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
@@ -41,10 +41,11 @@
#define FALCON_MAX_PAGE_SIZE EFHW_8K
/* include the register definitions */
-#include <ci/driver/efab/hardware/falcon/falcon_core.h>
+#ifdef USE_OLD_HWDEFS
+#include <ci/driver/efab/hardware/falcon/falcon_mac.h>
+#endif
#include <ci/driver/efab/hardware/falcon/falcon_desc.h>
#include <ci/driver/efab/hardware/falcon/falcon_event.h>
-#include <ci/driver/efab/hardware/falcon/falcon_mac.h>
#include <ci/driver/efab/hardware/falcon/falcon_grmon.h>
#include <ci/driver/efab/hardware/falcon/falcon_xgrmon.h>
#include <ci/driver/efab/hardware/falcon/falcon_intr_vec.h>
@@ -52,7 +53,6 @@
#define FALCON_DMA_TX_DESC_BYTES 8
#define FALCON_DMA_RX_PHYS_DESC_BYTES 8
#define FALCON_DMA_RX_BUF_DESC_BYTES 4
-
/* ---- efhw_event_t helpers --- */
@@ -77,6 +77,9 @@
#define FALCON_EVENT_RX_FLUSH_Q_ID_MASK \
(__FALCON_OPEN_MASK(DRIVER_EV_RX_DESCQ_ID_WIDTH) << \
DRIVER_EV_RX_DESCQ_ID_LBN)
+#define FALCON_EVENT_RX_FLUSH_FAIL_MASK \
+ (__FALCON_OPEN_MASK(DRIVER_EV_RX_FLUSH_FAIL_WIDTH) << \
+ DRIVER_EV_RX_FLUSH_FAIL_LBN)
#define FALCON_EVENT_DRV_SUBCODE_MASK \
(__FALCON_OPEN_MASK(DRIVER_EV_SUB_CODE_WIDTH) << \
DRIVER_EV_SUB_CODE_LBN)
@@ -95,6 +98,9 @@
#define FALCON_EVENT_RX_FLUSH_Q_ID(evp) \
(((evp)->u64 & FALCON_EVENT_RX_FLUSH_Q_ID_MASK) >> \
DRIVER_EV_RX_DESCQ_ID_LBN)
+#define FALCON_EVENT_RX_FLUSH_FAIL(evp) \
+ (((evp)->u64 & FALCON_EVENT_RX_FLUSH_FAIL_MASK) >> \
+ DRIVER_EV_RX_FLUSH_FAIL_LBN)
#define FALCON_EVENT_DRIVER_SUBCODE(evp) \
(((evp)->u64 & FALCON_EVENT_DRV_SUBCODE_MASK) >> \
DRIVER_EV_SUB_CODE_LBN)
@@ -143,15 +149,24 @@
*
*---------------------------------------------------------------------------*/
-#define FALCON_DMAQ_NUM (EFHW_4K)
-#define FALCON_EVQ_TBL_NUM (EFHW_4K)
-#define FALCON_TIMERS_NUM (EFHW_4K)
+/* Note: the following constants have moved to values in struct efhw_nic
+ * because they are different between Falcon and Siena:
+ * FALCON_EVQ_TBL_NUM -> nic->num_evqs
+ * FALCON_DMAQ_NUM -> nic->num_dmaqs
+ * FALCON_TIMERS_NUM -> nic->num_times
+ * These replacement constants are used as sanity checks in assertions in
+ * certain functions that don't have access to struct efhw_nic. They may
+ * catch some errors but do *not* guarantee a valid value for Siena.
+ */
+#define FALCON_DMAQ_NUM_SANITY (EFHW_4K)
+#define FALCON_EVQ_TBL_NUM_SANITY (EFHW_4K)
+#define FALCON_TIMERS_NUM_SANITY (EFHW_4K)
/* This value is an upper limit on the total number of filter table
- * entries, including odd and even banks. The actual size of filter table
- * is determined at runtime, as it can vary.
- */
-#define FALCON_FILTER_TBL_NUM (EFHW_16K)
+ * entries. The actual size of filter table is determined at runtime, as
+ * it can vary.
+ */
+#define FALCON_FILTER_TBL_NUM (EFHW_8K)
/* max number of buffers which can be pushed before commiting */
#define FALCON_BUFFER_UPD_MAX (128)
@@ -196,6 +211,9 @@ union __u64to32 {
} s;
};
+/* Ensure DW3 is written last. Outer locking cannot be relied upon to provide
+ * a write barrier
+ */
static inline void
falcon_write_ddd_d(volatile char __iomem *kva,
uint32_t d0, uint32_t d1, uint32_t d2, uint32_t d3)
@@ -205,8 +223,12 @@ falcon_write_ddd_d(volatile char __iomem
writel(d2, kva + 8);
mmiowb();
writel(d3, kva + 12);
-}
-
+ mmiowb();
+}
+
+/* Ensure DW3 is written last. Outer locking cannot be relied upon to provide
+ * a write barrier
+ */
static inline void falcon_write_q(volatile char __iomem *kva, uint64_t q)
{
union __u64to32 u;
@@ -215,6 +237,7 @@ static inline void falcon_write_q(volati
writel(u.s.a, kva);
mmiowb();
writel(u.s.b, kva + 4);
+ mmiowb();
}
static inline void falcon_read_q(volatile char __iomem *addr, uint64_t *q0)
@@ -224,9 +247,13 @@ static inline void falcon_read_q(volatil
* and we get a self consistent value.
*/
union __u64to32 u;
+ /* The CPU must always waits for a read to complete so locked sequences
+ * of reads cannot be interleaved. Lock is outside this function.
+ */
u.s.a = readl(addr);
- rmb();
+ rmb(); /* to stop compiler/CPU re-ordering these two reads*/
u.s.b = readl(addr + 4);
+ rmb(); /* just be safe: so falcon_read_q() can be composed */
*q0 = u.u64;
}
@@ -282,18 +309,23 @@ falcon_read_qq(volatile char __iomem *ad
static inline int falcon_timer_page_addr(uint idx)
{
-
- EFHW_ASSERT(TIMER_CMD_REG_KER_OFST ==
- (TIMER_CMD_REG_PAGE4_OFST - 4 * EFHW_8K));
-
- EFHW_ASSERT(idx < FALCON_TIMERS_NUM);
+#ifdef HEADER_REVIEW
+#warning TBD this needs more clean up; the function does not get a version
+#warning the function makes an index range check; this is device dependent
+#endif
+ EFHW_ASSERT(FR_AA_TIMER_COMMAND_REG_KER_OFST ==
+ (FR_AA_TIMER_COMMAND_REGP0_OFST - 4 * EFHW_8K));
+
+ EFHW_ASSERT(idx < FALCON_TIMERS_NUM_SANITY);
+ EFHW_ASSERT(FR_BZ_TIMER_COMMAND_REGP0_OFST==
+ FR_AA_TIMER_COMMAND_REG_KER_OFST);
if (idx < 4)
- return TIMER_CMD_REG_KER_OFST + (idx * EFHW_8K);
+ return FR_AA_TIMER_COMMAND_REG_KER_OFST + (idx * EFHW_8K);
else if (idx < 1024)
- return TIMER_CMD_REG_PAGE4_OFST + ((idx - 4) * EFHW_8K);
+ return FR_AA_TIMER_COMMAND_REGP0_OFST + ((idx - 4) * EFHW_8K);
else
- return TIMER_CMD_REG_PAGE123K_OFST + ((idx - 1024) * EFHW_8K);
+ return FR_AB_TIMER_COMMAND_REGP123_OFST + ((idx - 1024) *
EFHW_8K);
}
#define FALCON_TIMER_PAGE_MASK (EFHW_8K-1)
@@ -316,17 +348,21 @@ static inline uint falcon_tx_dma_page_ad
static inline uint falcon_tx_dma_page_addr(uint dmaq_idx)
{
uint page;
-
- EFHW_ASSERT((((TX_DESC_UPD_REG_PAGE123K_OFST) & (EFHW_8K - 1)) ==
- (((TX_DESC_UPD_REG_PAGE4_OFST) & (EFHW_8K - 1)))));
-
- EFHW_ASSERT(dmaq_idx < FALCON_DMAQ_NUM);
+#ifdef HEADER_REVIEW
+#warning TBD this needs more clean up; the function does not get a version
+#warning the function makes an index range check; this is device dependent
+#endif
+
+ EFHW_ASSERT((((FR_AB_TX_DESC_UPD_REGP123_OFST) & (EFHW_8K - 1)) ==
+ (((FR_AA_TX_DESC_UPD_REGP0_OFST) & (EFHW_8K - 1)))));
+
+ EFHW_ASSERT(dmaq_idx < FALCON_DMAQ_NUM_SANITY);
if (dmaq_idx < 1024)
- page = TX_DESC_UPD_REG_PAGE4_OFST + ((dmaq_idx - 4) * EFHW_8K);
+ page = FR_AA_TX_DESC_UPD_REGP0_OFST + ((dmaq_idx - 4) *
EFHW_8K);
else
page =
- TX_DESC_UPD_REG_PAGE123K_OFST +
+ FR_AB_TX_DESC_UPD_REGP123_OFST +
((dmaq_idx - 1024) * EFHW_8K);
return page;
@@ -336,17 +372,21 @@ static inline uint falcon_rx_dma_page_ad
static inline uint falcon_rx_dma_page_addr(uint dmaq_idx)
{
uint page;
-
- EFHW_ASSERT((((RX_DESC_UPD_REG_PAGE123K_OFST) & (EFHW_8K - 1)) ==
- ((RX_DESC_UPD_REG_PAGE4_OFST) & (EFHW_8K - 1))));
-
- EFHW_ASSERT(dmaq_idx < FALCON_DMAQ_NUM);
+#ifdef HEADER_REVIEW
+#warning TBD this needs more clean up; the function does not get a version
+#warning the function makes an index range check; this is device dependent
+#endif
+
+ EFHW_ASSERT((((FR_AB_RX_DESC_UPD_REGP123_OFST) & (EFHW_8K - 1)) ==
+ ((FR_AA_RX_DESC_UPD_REGP0_OFST) & (EFHW_8K - 1))));
+
+ EFHW_ASSERT(dmaq_idx < FALCON_DMAQ_NUM_SANITY);
if (dmaq_idx < 1024)
- page = RX_DESC_UPD_REG_PAGE4_OFST + ((dmaq_idx - 4) * EFHW_8K);
+ page = FR_AA_RX_DESC_UPD_REGP0_OFST + ((dmaq_idx - 4) *
EFHW_8K);
else
page =
- RX_DESC_UPD_REG_PAGE123K_OFST +
+ FR_AB_RX_DESC_UPD_REGP123_OFST +
((dmaq_idx - 1024) * EFHW_8K);
return page;
@@ -387,12 +427,7 @@ static inline int falcon_rx_dma_page_off
*
*---------------------------------------------------------------------------*/
-/* Falcon nails down the event queue mappings */
-#define FALCON_EVQ_KERNEL0 (0) /* hardwired for net driver */
-#define FALCON_EVQ_CHAR (4) /* char driver's event queue */
-
-/* reserved by the drivers */
-#define FALCON_EVQ_TBL_RESERVED (8)
+#define FALCON_A_EVQ_CHAR (4) /* min evq accessible via char bar */
/* default DMA-Q sizes */
#define FALCON_DMA_Q_DEFAULT_TX_SIZE 512
diff -r 0b5ca7cdbdfc -r b8c2a9aacba6
drivers/net/sfc/sfc_resource/ci/driver/efab/hardware/falcon/falcon_core.h
--- a/drivers/net/sfc/sfc_resource/ci/driver/efab/hardware/falcon/falcon_core.h
Fri Jan 08 13:05:49 2010 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,1149 +0,0 @@
-/****************************************************************************
- * Driver for Solarflare network controllers -
- * resource management for Xen backend, OpenOnload, etc
- * (including support for SFE4001 10GBT NIC)
- *
- * This file provides EtherFabric NIC - EFXXXX (aka Falcon) core register
- * definitions.
- *
- * Copyright 2005-2007: Solarflare Communications Inc,
- * 9501 Jeronimo Road, Suite 250,
- * Irvine, CA 92618, USA
- *
- * Developed and maintained by Solarflare Communications:
- * <linux-xen-drivers@xxxxxxxxxxxxxx>
- * <onload-dev@xxxxxxxxxxxxxx>
- *
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation, incorporated herein by reference.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- ****************************************************************************
- */
-
-#define FALCON_EXTENDED_P_BAR 1
-
-/*************---- Bus Interface Unit Registers C Header ----*************/
-#define IOM_IND_ADR_REG_OFST 0x0 /* IO-mapped indirect access address
- register */
- #define IOM_AUTO_ADR_INC_EN_LBN 16
- #define IOM_AUTO_ADR_INC_EN_WIDTH 1
- #define IOM_IND_ADR_LBN 0
- #define IOM_IND_ADR_WIDTH 16
-#define IOM_IND_DAT_REG_OFST 0x4 /* IO-mapped indirect access data register */
- #define IOM_IND_DAT_LBN 0
- #define IOM_IND_DAT_WIDTH 32
-#define ADR_REGION_REG_KER_OFST 0x0 /* Address region register */
-#define ADR_REGION_REG_OFST 0x0 /* Address region register */
- #define ADR_REGION3_LBN 96
- #define ADR_REGION3_WIDTH 18
- #define ADR_REGION2_LBN 64
- #define ADR_REGION2_WIDTH 18
- #define ADR_REGION1_LBN 32
- #define ADR_REGION1_WIDTH 18
- #define ADR_REGION0_LBN 0
- #define ADR_REGION0_WIDTH 18
-#define INT_EN_REG_KER_OFST 0x10 /* Kernel driver Interrupt enable register */
- #define KER_INT_CHAR_LBN 4
- #define KER_INT_CHAR_WIDTH 1
- #define KER_INT_KER_LBN 3
- #define KER_INT_KER_WIDTH 1
- #define ILL_ADR_ERR_INT_EN_KER_LBN 2
- #define ILL_ADR_ERR_INT_EN_KER_WIDTH 1
- #define SRM_PERR_INT_EN_KER_LBN 1
- #define SRM_PERR_INT_EN_KER_WIDTH 1
- #define DRV_INT_EN_KER_LBN 0
- #define DRV_INT_EN_KER_WIDTH 1
-#define INT_EN_REG_CHAR_OFST 0x20 /* Char Driver interrupt enable register */
- #define CHAR_INT_CHAR_LBN 4
- #define CHAR_INT_CHAR_WIDTH 1
- #define CHAR_INT_KER_LBN 3
- #define CHAR_INT_KER_WIDTH 1
- #define ILL_ADR_ERR_INT_EN_CHAR_LBN 2
- #define ILL_ADR_ERR_INT_EN_CHAR_WIDTH 1
- #define SRM_PERR_INT_EN_CHAR_LBN 1
- #define SRM_PERR_INT_EN_CHAR_WIDTH 1
- #define DRV_INT_EN_CHAR_LBN 0
- #define DRV_INT_EN_CHAR_WIDTH 1
-#define INT_ADR_REG_KER_OFST 0x30 /* Interrupt host address for Kernel driver
*/
- #define INT_ADR_KER_LBN 0
- #define INT_ADR_KER_WIDTH 64
- #define DRV_INT_KER_LBN 32
- #define DRV_INT_KER_WIDTH 1
- #define EV_FF_HALF_INT_KER_LBN 3
- #define EV_FF_HALF_INT_KER_WIDTH 1
- #define EV_FF_FULL_INT_KER_LBN 2
- #define EV_FF_FULL_INT_KER_WIDTH 1
- #define ILL_ADR_ERR_INT_KER_LBN 1
- #define ILL_ADR_ERR_INT_KER_WIDTH 1
- #define SRAM_PERR_INT_KER_LBN 0
- #define SRAM_PERR_INT_KER_WIDTH 1
-#define INT_ADR_REG_CHAR_OFST 0x40 /* Interrupt host address for Char driver */
- #define INT_ADR_CHAR_LBN 0
- #define INT_ADR_CHAR_WIDTH 64
- #define DRV_INT_CHAR_LBN 32
- #define DRV_INT_CHAR_WIDTH 1
- #define EV_FF_HALF_INT_CHAR_LBN 3
- #define EV_FF_HALF_INT_CHAR_WIDTH 1
- #define EV_FF_FULL_INT_CHAR_LBN 2
- #define EV_FF_FULL_INT_CHAR_WIDTH 1
- #define ILL_ADR_ERR_INT_CHAR_LBN 1
- #define ILL_ADR_ERR_INT_CHAR_WIDTH 1
- #define SRAM_PERR_INT_CHAR_LBN 0
- #define SRAM_PERR_INT_CHAR_WIDTH 1
-#define INT_ISR0_B0_OFST 0x90 /* B0 only */
-#define INT_ISR1_B0_OFST 0xA0
-#define INT_ACK_REG_KER_A1_OFST 0x50 /* Kernel interrupt acknowledge register
*/
- #define RESERVED_LBN 0
- #define RESERVED_WIDTH 32
-#define INT_ACK_REG_CHAR_A1_OFST 0x60 /* CHAR interrupt acknowledge register */
- #define RESERVED_LBN 0
- #define RESERVED_WIDTH 32
-/*************---- Global CSR Registers C Header ----*************/
-#define STRAP_REG_KER_OFST 0x200 /* ASIC strap status register */
-#define STRAP_REG_OFST 0x200 /* ASIC strap status register */
- #define ONCHIP_SRAM_LBN 16
- #define ONCHIP_SRAM_WIDTH 0
- #define STRAP_ISCSI_EN_LBN 3
- #define STRAP_ISCSI_EN_WIDTH 1
- #define STRAP_PINS_LBN 0
- #define STRAP_PINS_WIDTH 3
-#define GPIO_CTL_REG_KER_OFST 0x210 /* GPIO control register */
-#define GPIO_CTL_REG_OFST 0x210 /* GPIO control register */
- #define GPIO_OEN_LBN 24
- #define GPIO_OEN_WIDTH 4
- #define GPIO_OUT_LBN 16
- #define GPIO_OUT_WIDTH 4
- #define GPIO_IN_LBN 8
- #define GPIO_IN_WIDTH 4
- #define GPIO_PWRUP_VALUE_LBN 0
- #define GPIO_PWRUP_VALUE_WIDTH 4
-#define GLB_CTL_REG_KER_OFST 0x220 /* Global control register */
-#define GLB_CTL_REG_OFST 0x220 /* Global control register */
- #define SWRST_LBN 0
- #define SWRST_WIDTH 1
-#define FATAL_INTR_REG_KER_OFST 0x230 /* Fatal interrupt register for Kernel */
- #define PCI_BUSERR_INT_KER_EN_LBN 43
- #define PCI_BUSERR_INT_KER_EN_WIDTH 1
- #define SRAM_OOB_INT_KER_EN_LBN 42
- #define SRAM_OOB_INT_KER_EN_WIDTH 1
- #define BUFID_OOB_INT_KER_EN_LBN 41
- #define BUFID_OOB_INT_KER_EN_WIDTH 1
- #define MEM_PERR_INT_KER_EN_LBN 40
- #define MEM_PERR_INT_KER_EN_WIDTH 1
- #define RBUF_OWN_INT_KER_EN_LBN 39
- #define RBUF_OWN_INT_KER_EN_WIDTH 1
- #define TBUF_OWN_INT_KER_EN_LBN 38
- #define TBUF_OWN_INT_KER_EN_WIDTH 1
- #define RDESCQ_OWN_INT_KER_EN_LBN 37
- #define RDESCQ_OWN_INT_KER_EN_WIDTH 1
- #define TDESCQ_OWN_INT_KER_EN_LBN 36
- #define TDESCQ_OWN_INT_KER_EN_WIDTH 1
- #define EVQ_OWN_INT_KER_EN_LBN 35
- #define EVQ_OWN_INT_KER_EN_WIDTH 1
- #define EVFF_OFLO_INT_KER_EN_LBN 34
- #define EVFF_OFLO_INT_KER_EN_WIDTH 1
- #define ILL_ADR_INT_KER_EN_LBN 33
- #define ILL_ADR_INT_KER_EN_WIDTH 1
- #define SRM_PERR_INT_KER_EN_LBN 32
- #define SRM_PERR_INT_KER_EN_WIDTH 1
- #define PCI_BUSERR_INT_KER_LBN 11
- #define PCI_BUSERR_INT_KER_WIDTH 1
- #define SRAM_OOB_INT_KER_LBN 10
- #define SRAM_OOB_INT_KER_WIDTH 1
- #define BUFID_OOB_INT_KER_LBN 9
- #define BUFID_OOB_INT_KER_WIDTH 1
- #define MEM_PERR_INT_KER_LBN 8
- #define MEM_PERR_INT_KER_WIDTH 1
- #define RBUF_OWN_INT_KER_LBN 7
- #define RBUF_OWN_INT_KER_WIDTH 1
- #define TBUF_OWN_INT_KER_LBN 6
- #define TBUF_OWN_INT_KER_WIDTH 1
- #define RDESCQ_OWN_INT_KER_LBN 5
- #define RDESCQ_OWN_INT_KER_WIDTH 1
- #define TDESCQ_OWN_INT_KER_LBN 4
- #define TDESCQ_OWN_INT_KER_WIDTH 1
- #define EVQ_OWN_INT_KER_LBN 3
- #define EVQ_OWN_INT_KER_WIDTH 1
- #define EVFF_OFLO_INT_KER_LBN 2
- #define EVFF_OFLO_INT_KER_WIDTH 1
- #define ILL_ADR_INT_KER_LBN 1
- #define ILL_ADR_INT_KER_WIDTH 1
- #define SRM_PERR_INT_KER_LBN 0
- #define SRM_PERR_INT_KER_WIDTH 1
-#define FATAL_INTR_REG_OFST 0x240 /* Fatal interrupt register for Char */
- #define PCI_BUSERR_INT_CHAR_EN_LBN 43
- #define PCI_BUSERR_INT_CHAR_EN_WIDTH 1
- #define SRAM_OOB_INT_CHAR_EN_LBN 42
- #define SRAM_OOB_INT_CHAR_EN_WIDTH 1
- #define BUFID_OOB_INT_CHAR_EN_LBN 41
- #define BUFID_OOB_INT_CHAR_EN_WIDTH 1
- #define MEM_PERR_INT_CHAR_EN_LBN 40
- #define MEM_PERR_INT_CHAR_EN_WIDTH 1
- #define RBUF_OWN_INT_CHAR_EN_LBN 39
- #define RBUF_OWN_INT_CHAR_EN_WIDTH 1
- #define TBUF_OWN_INT_CHAR_EN_LBN 38
- #define TBUF_OWN_INT_CHAR_EN_WIDTH 1
- #define RDESCQ_OWN_INT_CHAR_EN_LBN 37
- #define RDESCQ_OWN_INT_CHAR_EN_WIDTH 1
- #define TDESCQ_OWN_INT_CHAR_EN_LBN 36
- #define TDESCQ_OWN_INT_CHAR_EN_WIDTH 1
- #define EVQ_OWN_INT_CHAR_EN_LBN 35
- #define EVQ_OWN_INT_CHAR_EN_WIDTH 1
- #define EVFF_OFLO_INT_CHAR_EN_LBN 34
- #define EVFF_OFLO_INT_CHAR_EN_WIDTH 1
- #define ILL_ADR_INT_CHAR_EN_LBN 33
- #define ILL_ADR_INT_CHAR_EN_WIDTH 1
- #define SRM_PERR_INT_CHAR_EN_LBN 32
- #define SRM_PERR_INT_CHAR_EN_WIDTH 1
- #define FATAL_INTR_REG_EN_BITS 0xffffffffffffffffULL
- #define PCI_BUSERR_INT_CHAR_LBN 11
- #define PCI_BUSERR_INT_CHAR_WIDTH 1
- #define SRAM_OOB_INT_CHAR_LBN 10
- #define SRAM_OOB_INT_CHAR_WIDTH 1
- #define BUFID_OOB_INT_CHAR_LBN 9
- #define BUFID_OOB_INT_CHAR_WIDTH 1
- #define MEM_PERR_INT_CHAR_LBN 8
- #define MEM_PERR_INT_CHAR_WIDTH 1
- #define RBUF_OWN_INT_CHAR_LBN 7
- #define RBUF_OWN_INT_CHAR_WIDTH 1
- #define TBUF_OWN_INT_CHAR_LBN 6
- #define TBUF_OWN_INT_CHAR_WIDTH 1
- #define RDESCQ_OWN_INT_CHAR_LBN 5
- #define RDESCQ_OWN_INT_CHAR_WIDTH 1
- #define TDESCQ_OWN_INT_CHAR_LBN 4
- #define TDESCQ_OWN_INT_CHAR_WIDTH 1
- #define EVQ_OWN_INT_CHAR_LBN 3
- #define EVQ_OWN_INT_CHAR_WIDTH 1
- #define EVFF_OFLO_INT_CHAR_LBN 2
- #define EVFF_OFLO_INT_CHAR_WIDTH 1
- #define ILL_ADR_INT_CHAR_LBN 1
- #define ILL_ADR_INT_CHAR_WIDTH 1
- #define SRM_PERR_INT_CHAR_LBN 0
- #define SRM_PERR_INT_CHAR_WIDTH 1
-#define DP_CTRL_REG_OFST 0x250 /* Datapath control register */
- #define FLS_EVQ_ID_LBN 0
- #define FLS_EVQ_ID_WIDTH 12
-#define MEM_STAT_REG_KER_OFST 0x260 /* Memory status register */
-#define MEM_STAT_REG_OFST 0x260 /* Memory status register */
- #define MEM_PERR_VEC_LBN 53
- #define MEM_PERR_VEC_WIDTH 38
- #define MBIST_CORR_LBN 38
- #define MBIST_CORR_WIDTH 15
- #define MBIST_ERR_LBN 0
- #define MBIST_ERR_WIDTH 38
-#define DEBUG_REG_KER_OFST 0x270 /* Debug register */
-#define DEBUG_REG_OFST 0x270 /* Debug register */
- #define DEBUG_BLK_SEL2_LBN 47
- #define DEBUG_BLK_SEL2_WIDTH 3
- #define DEBUG_BLK_SEL1_LBN 44
- #define DEBUG_BLK_SEL1_WIDTH 3
- #define DEBUG_BLK_SEL0_LBN 41
- #define DEBUG_BLK_SEL0_WIDTH 3
- #define MISC_DEBUG_ADDR_LBN 36
- #define MISC_DEBUG_ADDR_WIDTH 5
- #define SERDES_DEBUG_ADDR_LBN 31
- #define SERDES_DEBUG_ADDR_WIDTH 5
- #define EM_DEBUG_ADDR_LBN 26
- #define EM_DEBUG_ADDR_WIDTH 5
- #define SR_DEBUG_ADDR_LBN 21
- #define SR_DEBUG_ADDR_WIDTH 5
- #define EV_DEBUG_ADDR_LBN 16
- #define EV_DEBUG_ADDR_WIDTH 5
- #define RX_DEBUG_ADDR_LBN 11
- #define RX_DEBUG_ADDR_WIDTH 5
- #define TX_DEBUG_ADDR_LBN 6
- #define TX_DEBUG_ADDR_WIDTH 5
- #define BIU_DEBUG_ADDR_LBN 1
- #define BIU_DEBUG_ADDR_WIDTH 5
- #define DEBUG_EN_LBN 0
- #define DEBUG_EN_WIDTH 1
-#define DRIVER_REG0_KER_OFST 0x280 /* Driver scratch register 0 */
-#define DRIVER_REG0_OFST 0x280 /* Driver scratch register 0 */
- #define DRIVER_DW0_LBN 0
- #define DRIVER_DW0_WIDTH 32
-#define DRIVER_REG1_KER_OFST 0x290 /* Driver scratch register 1 */
-#define DRIVER_REG1_OFST 0x290 /* Driver scratch register 1 */
- #define DRIVER_DW1_LBN 0
- #define DRIVER_DW1_WIDTH 32
-#define DRIVER_REG2_KER_OFST 0x2A0 /* Driver scratch register 2 */
-#define DRIVER_REG2_OFST 0x2A0 /* Driver scratch register 2 */
- #define DRIVER_DW2_LBN 0
- #define DRIVER_DW2_WIDTH 32
-#define DRIVER_REG3_KER_OFST 0x2B0 /* Driver scratch register 3 */
-#define DRIVER_REG3_OFST 0x2B0 /* Driver scratch register 3 */
- #define DRIVER_DW3_LBN 0
- #define DRIVER_DW3_WIDTH 32
-#define DRIVER_REG4_KER_OFST 0x2C0 /* Driver scratch register 4 */
-#define DRIVER_REG4_OFST 0x2C0 /* Driver scratch register 4 */
- #define DRIVER_DW4_LBN 0
- #define DRIVER_DW4_WIDTH 32
-#define DRIVER_REG5_KER_OFST 0x2D0 /* Driver scratch register 5 */
-#define DRIVER_REG5_OFST 0x2D0 /* Driver scratch register 5 */
- #define DRIVER_DW5_LBN 0
- #define DRIVER_DW5_WIDTH 32
-#define DRIVER_REG6_KER_OFST 0x2E0 /* Driver scratch register 6 */
-#define DRIVER_REG6_OFST 0x2E0 /* Driver scratch register 6 */
- #define DRIVER_DW6_LBN 0
- #define DRIVER_DW6_WIDTH 32
-#define DRIVER_REG7_KER_OFST 0x2F0 /* Driver scratch register 7 */
-#define DRIVER_REG7_OFST 0x2F0 /* Driver scratch register 7 */
- #define DRIVER_DW7_LBN 0
- #define DRIVER_DW7_WIDTH 32
-#define ALTERA_BUILD_REG_OFST 0x300 /* Altera build register */
-#define ALTERA_BUILD_REG_OFST 0x300 /* Altera build register */
- #define ALTERA_BUILD_VER_LBN 0
- #define ALTERA_BUILD_VER_WIDTH 32
-
-/* so called CSR spare register
- - contains separate parity enable bits for the various internal memory
- blocks */
-#define MEM_PARITY_ERR_EN_REG_KER 0x310
-#define MEM_PARITY_ALL_BLOCKS_EN_LBN 64
-#define MEM_PARITY_ALL_BLOCKS_EN_WIDTH 38
-#define MEM_PARITY_TX_DATA_EN_LBN 72
-#define MEM_PARITY_TX_DATA_EN_WIDTH 2
-
-/*************---- Event & Timer Module Registers C Header ----*************/
-
-#if FALCON_EXTENDED_P_BAR
-#define EVQ_RPTR_REG_KER_OFST 0x11B00 /* Event queue read pointer register */
-#else
-#define EVQ_RPTR_REG_KER_OFST 0x1B00 /* Event queue read pointer register */
-#endif
-
-#define EVQ_RPTR_REG_OFST 0xFA0000 /* Event queue read pointer register
- array. */
- #define EVQ_RPTR_LBN 0
- #define EVQ_RPTR_WIDTH 15
-
-#if FALCON_EXTENDED_P_BAR
-#define EVQ_PTR_TBL_KER_OFST 0x11A00 /* Event queue pointer table for kernel
- access */
-#else
-#define EVQ_PTR_TBL_KER_OFST 0x1A00 /* Event queue pointer table for kernel
- access */
-#endif
-
-#define EVQ_PTR_TBL_CHAR_OFST 0xF60000 /* Event queue pointer table for char
- direct access */
- #define EVQ_WKUP_OR_INT_EN_LBN 39
- #define EVQ_WKUP_OR_INT_EN_WIDTH 1
- #define EVQ_NXT_WPTR_LBN 24
- #define EVQ_NXT_WPTR_WIDTH 15
- #define EVQ_EN_LBN 23
- #define EVQ_EN_WIDTH 1
- #define EVQ_SIZE_LBN 20
- #define EVQ_SIZE_WIDTH 3
- #define EVQ_BUF_BASE_ID_LBN 0
- #define EVQ_BUF_BASE_ID_WIDTH 20
-#define TIMER_CMD_REG_KER_OFST 0x420 /* Timer table for kernel access.
- Page-mapped */
-#define TIMER_CMD_REG_PAGE4_OFST 0x8420 /* Timer table for user-level access.
- Page-mapped. For lowest 1K queues.
- */
-#define TIMER_CMD_REG_PAGE123K_OFST 0x1000420 /* Timer table for user-level
- access. Page-mapped.
- For upper 3K queues. */
-#define TIMER_TBL_OFST 0xF70000 /* Timer table for char driver direct access */
- #define TIMER_MODE_LBN 12
- #define TIMER_MODE_WIDTH 2
- #define TIMER_VAL_LBN 0
- #define TIMER_VAL_WIDTH 12
- #define TIMER_MODE_INT_HLDOFF 2
- #define EVQ_BUF_SIZE_LBN 0
- #define EVQ_BUF_SIZE_WIDTH 1
-#define DRV_EV_REG_KER_OFST 0x440 /* Driver generated event register */
-#define DRV_EV_REG_OFST 0x440 /* Driver generated event register */
- #define DRV_EV_QID_LBN 64
- #define DRV_EV_QID_WIDTH 12
- #define DRV_EV_DATA_LBN 0
- #define DRV_EV_DATA_WIDTH 64
-#define EVQ_CTL_REG_KER_OFST 0x450 /* Event queue control register */
-#define EVQ_CTL_REG_OFST 0x450 /* Event queue control register */
- #define RX_EVQ_WAKEUP_MASK_B0_LBN 15
- #define RX_EVQ_WAKEUP_MASK_B0_WIDTH 6
- #define EVQ_OWNERR_CTL_LBN 14
- #define EVQ_OWNERR_CTL_WIDTH 1
- #define EVQ_FIFO_AF_TH_LBN 8
- #define EVQ_FIFO_AF_TH_WIDTH 6
- #define EVQ_FIFO_NOTAF_TH_LBN 0
- #define EVQ_FIFO_NOTAF_TH_WIDTH 6
-/*************---- SRAM Module Registers C Header ----*************/
-#define BUF_TBL_CFG_REG_KER_OFST 0x600 /* Buffer table configuration register
*/
-#define BUF_TBL_CFG_REG_OFST 0x600 /* Buffer table configuration register */
- #define BUF_TBL_MODE_LBN 3
- #define BUF_TBL_MODE_WIDTH 1
-#define SRM_RX_DC_CFG_REG_KER_OFST 0x610 /* SRAM receive descriptor cache
- configuration register */
-#define SRM_RX_DC_CFG_REG_OFST 0x610 /* SRAM receive descriptor cache
- configuration register */
- #define SRM_RX_DC_BASE_ADR_LBN 0
- #define SRM_RX_DC_BASE_ADR_WIDTH 21
-#define SRM_TX_DC_CFG_REG_KER_OFST 0x620 /* SRAM transmit descriptor cache
- configuration register */
-#define SRM_TX_DC_CFG_REG_OFST 0x620 /* SRAM transmit descriptor cache
- configuration register */
- #define SRM_TX_DC_BASE_ADR_LBN 0
- #define SRM_TX_DC_BASE_ADR_WIDTH 21
-#define SRM_CFG_REG_KER_OFST 0x630 /* SRAM configuration register */
-#define SRM_CFG_REG_OFST 0x630 /* SRAM configuration register */
- #define SRAM_OOB_ADR_INTEN_LBN 5
- #define SRAM_OOB_ADR_INTEN_WIDTH 1
- #define SRAM_OOB_BUF_INTEN_LBN 4
- #define SRAM_OOB_BUF_INTEN_WIDTH 1
- #define SRAM_BT_INIT_EN_LBN 3
- #define SRAM_BT_INIT_EN_WIDTH 1
- #define SRM_NUM_BANK_LBN 2
- #define SRM_NUM_BANK_WIDTH 1
- #define SRM_BANK_SIZE_LBN 0
- #define SRM_BANK_SIZE_WIDTH 2
-#define BUF_TBL_UPD_REG_KER_OFST 0x650 /* Buffer table update register */
-#define BUF_TBL_UPD_REG_OFST 0x650 /* Buffer table update register */
- #define BUF_UPD_CMD_LBN 63
- #define BUF_UPD_CMD_WIDTH 1
- #define BUF_CLR_CMD_LBN 62
- #define BUF_CLR_CMD_WIDTH 1
- #define BUF_CLR_END_ID_LBN 32
- #define BUF_CLR_END_ID_WIDTH 20
- #define BUF_CLR_START_ID_LBN 0
- #define BUF_CLR_START_ID_WIDTH 20
-#define SRM_UPD_EVQ_REG_KER_OFST 0x660 /* Buffer table update register */
-#define SRM_UPD_EVQ_REG_OFST 0x660 /* Buffer table update register */
- #define SRM_UPD_EVQ_ID_LBN 0
- #define SRM_UPD_EVQ_ID_WIDTH 12
-#define SRAM_PARITY_REG_KER_OFST 0x670 /* SRAM parity register. */
-#define SRAM_PARITY_REG_OFST 0x670 /* SRAM parity register. */
- #define FORCE_SRAM_PERR_LBN 0
- #define FORCE_SRAM_PERR_WIDTH 1
-
-#if FALCON_EXTENDED_P_BAR
-#define BUF_HALF_TBL_KER_OFST 0x18000 /* Buffer table in half buffer table
- mode direct access by kernel driver */
-#else
-#define BUF_HALF_TBL_KER_OFST 0x8000 /* Buffer table in half buffer table
- mode direct access by kernel driver */
-#endif
-
-
-#define BUF_HALF_TBL_OFST 0x800000 /* Buffer table in half buffer table mode
- direct access by char driver */
- #define BUF_ADR_HBUF_ODD_LBN 44
- #define BUF_ADR_HBUF_ODD_WIDTH 20
- #define BUF_OWNER_ID_HBUF_ODD_LBN 32
- #define BUF_OWNER_ID_HBUF_ODD_WIDTH 12
- #define BUF_ADR_HBUF_EVEN_LBN 12
- #define BUF_ADR_HBUF_EVEN_WIDTH 20
- #define BUF_OWNER_ID_HBUF_EVEN_LBN 0
- #define BUF_OWNER_ID_HBUF_EVEN_WIDTH 12
-
-
-#if FALCON_EXTENDED_P_BAR
-#define BUF_FULL_TBL_KER_OFST 0x18000 /* Buffer table in full buffer table
- mode direct access by kernel driver */
-#else
-#define BUF_FULL_TBL_KER_OFST 0x8000 /* Buffer table in full buffer table mode
- direct access by kernel driver */
-#endif
-
-
-
-
-#define BUF_FULL_TBL_OFST 0x800000 /* Buffer table in full buffer table mode
- direct access by char driver */
- #define IP_DAT_BUF_SIZE_LBN 50
- #define IP_DAT_BUF_SIZE_WIDTH 1
- #define BUF_ADR_REGION_LBN 48
- #define BUF_ADR_REGION_WIDTH 2
- #define BUF_ADR_FBUF_LBN 14
- #define BUF_ADR_FBUF_WIDTH 34
- #define BUF_OWNER_ID_FBUF_LBN 0
- #define BUF_OWNER_ID_FBUF_WIDTH 14
-#define SRM_DBG_REG_OFST 0x3000000 /* SRAM debug access */
- #define SRM_DBG_LBN 0
- #define SRM_DBG_WIDTH 64
-/*************---- RX Datapath Registers C Header ----*************/
-
-#define RX_CFG_REG_KER_OFST 0x800 /* Receive configuration register */
-#define RX_CFG_REG_OFST 0x800 /* Receive configuration register */
-
-#if !defined(FALCON_64K_RXFIFO) && !defined(FALCON_PRE_02020029)
-# if !defined(FALCON_128K_RXFIFO)
-# define FALCON_128K_RXFIFO
-# endif
-#endif
-
-#if defined(FALCON_128K_RXFIFO)
-
-/* new for B0 */
- #define RX_TOEP_TCP_SUPPRESS_B0_LBN 48
- #define RX_TOEP_TCP_SUPPRESS_B0_WIDTH 1
- #define RX_INGR_EN_B0_LBN 47
- #define RX_INGR_EN_B0_WIDTH 1
- #define RX_TOEP_IPV4_B0_LBN 46
- #define RX_TOEP_IPV4_B0_WIDTH 1
- #define RX_HASH_ALG_B0_LBN 45
- #define RX_HASH_ALG_B0_WIDTH 1
- #define RX_HASH_INSERT_HDR_B0_LBN 44
- #define RX_HASH_INSERT_HDR_B0_WIDTH 1
-/* moved for B0 */
- #define RX_DESC_PUSH_EN_B0_LBN 43
- #define RX_DESC_PUSH_EN_B0_WIDTH 1
- #define RX_RDW_PATCH_EN_LBN 42 /* Non head of line blocking */
- #define RX_RDW_PATCH_EN_WIDTH 1
- #define RX_PCI_BURST_SIZE_B0_LBN 39
- #define RX_PCI_BURST_SIZE_B0_WIDTH 3
- #define RX_OWNERR_CTL_B0_LBN 38
- #define RX_OWNERR_CTL_B0_WIDTH 1
- #define RX_XON_TX_TH_B0_LBN 33
- #define RX_XON_TX_TH_B0_WIDTH 5
- #define RX_XOFF_TX_TH_B0_LBN 28
- #define RX_XOFF_TX_TH_B0_WIDTH 5
- #define RX_USR_BUF_SIZE_B0_LBN 19
- #define RX_USR_BUF_SIZE_B0_WIDTH 9
- #define RX_XON_MAC_TH_B0_LBN 10
- #define RX_XON_MAC_TH_B0_WIDTH 9
- #define RX_XOFF_MAC_TH_B0_LBN 1
- #define RX_XOFF_MAC_TH_B0_WIDTH 9
- #define RX_XOFF_MAC_EN_B0_LBN 0
- #define RX_XOFF_MAC_EN_B0_WIDTH 1
-
-#elif !defined(FALCON_PRE_02020029)
-/* new for B0 */
- #define RX_TOEP_TCP_SUPPRESS_B0_LBN 46
- #define RX_TOEP_TCP_SUPPRESS_B0_WIDTH 1
- #define RX_INGR_EN_B0_LBN 45
- #define RX_INGR_EN_B0_WIDTH 1
- #define RX_TOEP_IPV4_B0_LBN 44
- #define RX_TOEP_IPV4_B0_WIDTH 1
- #define RX_HASH_ALG_B0_LBN 43
- #define RX_HASH_ALG_B0_WIDTH 41
- #define RX_HASH_INSERT_HDR_B0_LBN 42
- #define RX_HASH_INSERT_HDR_B0_WIDTH 1
-/* moved for B0 */
- #define RX_DESC_PUSH_EN_B0_LBN 41
- #define RX_DESC_PUSH_EN_B0_WIDTH 1
- #define RX_PCI_BURST_SIZE_B0_LBN 37
- #define RX_PCI_BURST_SIZE_B0_WIDTH 3
- #define RX_OWNERR_CTL_B0_LBN 36
- #define RX_OWNERR_CTL_B0_WIDTH 1
- #define RX_XON_TX_TH_B0_LBN 31
- #define RX_XON_TX_TH_B0_WIDTH 5
- #define RX_XOFF_TX_TH_B0_LBN 26
- #define RX_XOFF_TX_TH_B0_WIDTH 5
- #define RX_USR_BUF_SIZE_B0_LBN 17
- #define RX_USR_BUF_SIZE_B0_WIDTH 9
- #define RX_XON_MAC_TH_B0_LBN 9
- #define RX_XON_MAC_TH_B0_WIDTH 8
- #define RX_XOFF_MAC_TH_B0_LBN 1
- #define RX_XOFF_MAC_TH_B0_WIDTH 8
- #define RX_XOFF_MAC_EN_B0_LBN 0
- #define RX_XOFF_MAC_EN_B0_WIDTH 1
-
-#else
-/* new for B0 */
- #define RX_TOEP_TCP_SUPPRESS_B0_LBN 44
- #define RX_TOEP_TCP_SUPPRESS_B0_WIDTH 1
- #define RX_INGR_EN_B0_LBN 43
- #define RX_INGR_EN_B0_WIDTH 1
- #define RX_TOEP_IPV4_B0_LBN 42
- #define RX_TOEP_IPV4_B0_WIDTH 1
- #define RX_HASH_ALG_B0_LBN 41
- #define RX_HASH_ALG_B0_WIDTH 41
- #define RX_HASH_INSERT_HDR_B0_LBN 40
- #define RX_HASH_INSERT_HDR_B0_WIDTH 1
-/* moved for B0 */
- #define RX_DESC_PUSH_EN_B0_LBN 35
- #define RX_DESC_PUSH_EN_B0_WIDTH 1
- #define RX_PCI_BURST_SIZE_B0_LBN 35
- #define RX_PCI_BURST_SIZE_B0_WIDTH 2
- #define RX_OWNERR_CTL_B0_LBN 34
- #define RX_OWNERR_CTL_B0_WIDTH 1
- #define RX_XON_TX_TH_B0_LBN 29
- #define RX_XON_TX_TH_B0_WIDTH 5
- #define RX_XOFF_TX_TH_B0_LBN 24
- #define RX_XOFF_TX_TH_B0_WIDTH 5
- #define RX_USR_BUF_SIZE_B0_LBN 15
- #define RX_USR_BUF_SIZE_B0_WIDTH 9
- #define RX_XON_MAC_TH_B0_LBN 8
- #define RX_XON_MAC_TH_B0_WIDTH 7
- #define RX_XOFF_MAC_TH_B0_LBN 1
- #define RX_XOFF_MAC_TH_B0_WIDTH 7
- #define RX_XOFF_MAC_EN_B0_LBN 0
- #define RX_XOFF_MAC_EN_B0_WIDTH 1
-
-#endif
-
-/* A0/A1 */
- #define RX_PUSH_EN_A1_LBN 35
- #define RX_PUSH_EN_A1_WIDTH 1
- #define RX_PCI_BURST_SIZE_A1_LBN 31
- #define RX_PCI_BURST_SIZE_A1_WIDTH 3
- #define RX_OWNERR_CTL_A1_LBN 30
- #define RX_OWNERR_CTL_A1_WIDTH 1
- #define RX_XON_TX_TH_A1_LBN 25
- #define RX_XON_TX_TH_A1_WIDTH 5
- #define RX_XOFF_TX_TH_A1_LBN 20
- #define RX_XOFF_TX_TH_A1_WIDTH 5
- #define RX_USR_BUF_SIZE_A1_LBN 11
- #define RX_USR_BUF_SIZE_A1_WIDTH 9
- #define RX_XON_MAC_TH_A1_LBN 6
- #define RX_XON_MAC_TH_A1_WIDTH 5
- #define RX_XOFF_MAC_TH_A1_LBN 1
- #define RX_XOFF_MAC_TH_A1_WIDTH 5
- #define RX_XOFF_MAC_EN_A1_LBN 0
- #define RX_XOFF_MAC_EN_A1_WIDTH 1
-
-#define RX_FILTER_CTL_REG_OFST 0x810 /* Receive filter control registers */
- #define SCATTER_ENBL_NO_MATCH_Q_B0_LBN 40
- #define SCATTER_ENBL_NO_MATCH_Q_B0_WIDTH 1
- #define UDP_FULL_SRCH_LIMIT_LBN 32
- #define UDP_FULL_SRCH_LIMIT_WIDTH 8
- #define NUM_KER_LBN 24
- #define NUM_KER_WIDTH 2
- #define UDP_WILD_SRCH_LIMIT_LBN 16
- #define UDP_WILD_SRCH_LIMIT_WIDTH 8
- #define TCP_WILD_SRCH_LIMIT_LBN 8
- #define TCP_WILD_SRCH_LIMIT_WIDTH 8
- #define TCP_FULL_SRCH_LIMIT_LBN 0
- #define TCP_FULL_SRCH_LIMIT_WIDTH 8
-#define RX_FLUSH_DESCQ_REG_KER_OFST 0x820 /* Receive flush descriptor queue
- register */
-#define RX_FLUSH_DESCQ_REG_OFST 0x820 /* Receive flush descriptor queue
- register */
- #define RX_FLUSH_DESCQ_CMD_LBN 24
- #define RX_FLUSH_DESCQ_CMD_WIDTH 1
- #define RX_FLUSH_EVQ_ID_LBN 12
- #define RX_FLUSH_EVQ_ID_WIDTH 12
- #define RX_FLUSH_DESCQ_LBN 0
- #define RX_FLUSH_DESCQ_WIDTH 12
-#define RX_DESC_UPD_REG_KER_OFST 0x830 /* Kernel receive descriptor update
- register. Page-mapped */
-#define RX_DESC_UPD_REG_PAGE4_OFST 0x8830 /* Char & user receive descriptor
- update register. Page-mapped.
- For lowest 1K queues. */
-#define RX_DESC_UPD_REG_PAGE123K_OFST 0x1000830 /* Char & user receive
- descriptor update register.
- Page-mapped. For upper
- 3K queues. */
- #define RX_DESC_WPTR_LBN 96
- #define RX_DESC_WPTR_WIDTH 12
- #define RX_DESC_PUSH_CMD_LBN 95
- #define RX_DESC_PUSH_CMD_WIDTH 1
- #define RX_DESC_LBN 0
- #define RX_DESC_WIDTH 64
- #define RX_KER_DESC_LBN 0
- #define RX_KER_DESC_WIDTH 64
- #define RX_USR_DESC_LBN 0
- #define RX_USR_DESC_WIDTH 32
-#define RX_DC_CFG_REG_KER_OFST 0x840 /* Receive descriptor cache
- configuration register */
-#define RX_DC_CFG_REG_OFST 0x840 /* Receive descriptor cache
- configuration register */
- #define RX_DC_SIZE_LBN 0
- #define RX_DC_SIZE_WIDTH 2
-#define RX_DC_PF_WM_REG_KER_OFST 0x850 /* Receive descriptor cache pre-fetch
- watermark register */
-#define RX_DC_PF_WM_REG_OFST 0x850 /* Receive descriptor cache pre-fetch
- watermark register */
- #define RX_DC_PF_LWM_LO_LBN 0
- #define RX_DC_PF_LWM_LO_WIDTH 6
-
-#define RX_RSS_TKEY_B0_OFST 0x860 /* RSS Toeplitz hash key (B0 only) */
-
-#define RX_NODESC_DROP_REG 0x880
- #define RX_NODESC_DROP_CNT_LBN 0
- #define RX_NODESC_DROP_CNT_WIDTH 16
-
-#define XM_TX_CFG_REG_OFST 0x1230
- #define XM_AUTO_PAD_LBN 5
- #define XM_AUTO_PAD_WIDTH 1
-
-#define RX_FILTER_TBL0_OFST 0xF00000 /* Receive filter table - even entries */
- #define RSS_EN_0_B0_LBN 110
- #define RSS_EN_0_B0_WIDTH 1
- #define SCATTER_EN_0_B0_LBN 109
- #define SCATTER_EN_0_B0_WIDTH 1
- #define TCP_UDP_0_LBN 108
- #define TCP_UDP_0_WIDTH 1
- #define RXQ_ID_0_LBN 96
- #define RXQ_ID_0_WIDTH 12
- #define DEST_IP_0_LBN 64
- #define DEST_IP_0_WIDTH 32
- #define DEST_PORT_TCP_0_LBN 48
- #define DEST_PORT_TCP_0_WIDTH 16
- #define SRC_IP_0_LBN 16
- #define SRC_IP_0_WIDTH 32
- #define SRC_TCP_DEST_UDP_0_LBN 0
- #define SRC_TCP_DEST_UDP_0_WIDTH 16
-#define RX_FILTER_TBL1_OFST 0xF00010 /* Receive filter table - odd entries */
- #define RSS_EN_1_B0_LBN 110
- #define RSS_EN_1_B0_WIDTH 1
- #define SCATTER_EN_1_B0_LBN 109
- #define SCATTER_EN_1_B0_WIDTH 1
- #define TCP_UDP_1_LBN 108
- #define TCP_UDP_1_WIDTH 1
- #define RXQ_ID_1_LBN 96
- #define RXQ_ID_1_WIDTH 12
- #define DEST_IP_1_LBN 64
- #define DEST_IP_1_WIDTH 32
- #define DEST_PORT_TCP_1_LBN 48
- #define DEST_PORT_TCP_1_WIDTH 16
- #define SRC_IP_1_LBN 16
- #define SRC_IP_1_WIDTH 32
- #define SRC_TCP_DEST_UDP_1_LBN 0
- #define SRC_TCP_DEST_UDP_1_WIDTH 16
-
-#if FALCON_EXTENDED_P_BAR
-#define RX_DESC_PTR_TBL_KER_OFST 0x11800 /* Receive descriptor pointer
- kernel access */
-#else
-#define RX_DESC_PTR_TBL_KER_OFST 0x1800 /* Receive descriptor pointer
- kernel access */
-#endif
-
-
-#define RX_DESC_PTR_TBL_OFST 0xF40000 /* Receive descriptor pointer table */
- #define RX_ISCSI_DDIG_EN_LBN 88
- #define RX_ISCSI_DDIG_EN_WIDTH 1
- #define RX_ISCSI_HDIG_EN_LBN 87
- #define RX_ISCSI_HDIG_EN_WIDTH 1
- #define RX_DESC_PREF_ACT_LBN 86
- #define RX_DESC_PREF_ACT_WIDTH 1
- #define RX_DC_HW_RPTR_LBN 80
- #define RX_DC_HW_RPTR_WIDTH 6
- #define RX_DESCQ_HW_RPTR_LBN 68
- #define RX_DESCQ_HW_RPTR_WIDTH 12
- #define RX_DESCQ_SW_WPTR_LBN 56
- #define RX_DESCQ_SW_WPTR_WIDTH 12
- #define RX_DESCQ_BUF_BASE_ID_LBN 36
- #define RX_DESCQ_BUF_BASE_ID_WIDTH 20
- #define RX_DESCQ_EVQ_ID_LBN 24
- #define RX_DESCQ_EVQ_ID_WIDTH 12
- #define RX_DESCQ_OWNER_ID_LBN 10
- #define RX_DESCQ_OWNER_ID_WIDTH 14
- #define RX_DESCQ_LABEL_LBN 5
- #define RX_DESCQ_LABEL_WIDTH 5
- #define RX_DESCQ_SIZE_LBN 3
- #define RX_DESCQ_SIZE_WIDTH 2
- #define RX_DESCQ_TYPE_LBN 2
- #define RX_DESCQ_TYPE_WIDTH 1
- #define RX_DESCQ_JUMBO_LBN 1
- #define RX_DESCQ_JUMBO_WIDTH 1
- #define RX_DESCQ_EN_LBN 0
- #define RX_DESCQ_EN_WIDTH 1
-
-
-#define RX_RSS_INDIR_TBL_B0_OFST 0xFB0000 /* RSS indirection table (B0 only) */
- #define RX_RSS_INDIR_ENT_B0_LBN 0
- #define RX_RSS_INDIR_ENT_B0_WIDTH 6
-
-/*************---- TX Datapath Registers C Header ----*************/
-#define TX_FLUSH_DESCQ_REG_KER_OFST 0xA00 /* Transmit flush descriptor
- queue register */
-#define TX_FLUSH_DESCQ_REG_OFST 0xA00 /* Transmit flush descriptor queue
- register */
- #define TX_FLUSH_DESCQ_CMD_LBN 12
- #define TX_FLUSH_DESCQ_CMD_WIDTH 1
- #define TX_FLUSH_DESCQ_LBN 0
- #define TX_FLUSH_DESCQ_WIDTH 12
-#define TX_DESC_UPD_REG_KER_OFST 0xA10 /* Kernel transmit descriptor update
- register. Page-mapped */
-#define TX_DESC_UPD_REG_PAGE4_OFST 0x8A10 /* Char & user transmit descriptor
- update register. Page-mapped */
-#define TX_DESC_UPD_REG_PAGE123K_OFST 0x1000A10 /* Char & user transmit
- descriptor update register.
- Page-mapped */
- #define TX_DESC_WPTR_LBN 96
- #define TX_DESC_WPTR_WIDTH 12
- #define TX_DESC_PUSH_CMD_LBN 95
- #define TX_DESC_PUSH_CMD_WIDTH 1
- #define TX_DESC_LBN 0
- #define TX_DESC_WIDTH 95
- #define TX_KER_DESC_LBN 0
- #define TX_KER_DESC_WIDTH 64
- #define TX_USR_DESC_LBN 0
- #define TX_USR_DESC_WIDTH 64
-#define TX_DC_CFG_REG_KER_OFST 0xA20 /* Transmit descriptor cache
- configuration register */
-#define TX_DC_CFG_REG_OFST 0xA20 /* Transmit descriptor cache configuration
- register */
- #define TX_DC_SIZE_LBN 0
- #define TX_DC_SIZE_WIDTH 2
-
-#if FALCON_EXTENDED_P_BAR
-#define TX_DESC_PTR_TBL_KER_OFST 0x11900 /* Transmit descriptor pointer. */
-#else
-#define TX_DESC_PTR_TBL_KER_OFST 0x1900 /* Transmit descriptor pointer. */
-#endif
-
-
-#define TX_DESC_PTR_TBL_OFST 0xF50000 /* Transmit descriptor pointer */
- #define TX_NON_IP_DROP_DIS_B0_LBN 91
- #define TX_NON_IP_DROP_DIS_B0_WIDTH 1
- #define TX_IP_CHKSM_DIS_B0_LBN 90
- #define TX_IP_CHKSM_DIS_B0_WIDTH 1
- #define TX_TCP_CHKSM_DIS_B0_LBN 89
- #define TX_TCP_CHKSM_DIS_B0_WIDTH 1
- #define TX_DESCQ_EN_LBN 88
- #define TX_DESCQ_EN_WIDTH 1
- #define TX_ISCSI_DDIG_EN_LBN 87
- #define TX_ISCSI_DDIG_EN_WIDTH 1
- #define TX_ISCSI_HDIG_EN_LBN 86
- #define TX_ISCSI_HDIG_EN_WIDTH 1
- #define TX_DC_HW_RPTR_LBN 80
- #define TX_DC_HW_RPTR_WIDTH 6
- #define TX_DESCQ_HW_RPTR_LBN 68
- #define TX_DESCQ_HW_RPTR_WIDTH 12
- #define TX_DESCQ_SW_WPTR_LBN 56
- #define TX_DESCQ_SW_WPTR_WIDTH 12
- #define TX_DESCQ_BUF_BASE_ID_LBN 36
- #define TX_DESCQ_BUF_BASE_ID_WIDTH 20
- #define TX_DESCQ_EVQ_ID_LBN 24
- #define TX_DESCQ_EVQ_ID_WIDTH 12
- #define TX_DESCQ_OWNER_ID_LBN 10
- #define TX_DESCQ_OWNER_ID_WIDTH 14
- #define TX_DESCQ_LABEL_LBN 5
- #define TX_DESCQ_LABEL_WIDTH 5
- #define TX_DESCQ_SIZE_LBN 3
- #define TX_DESCQ_SIZE_WIDTH 2
- #define TX_DESCQ_TYPE_LBN 1
- #define TX_DESCQ_TYPE_WIDTH 2
- #define TX_DESCQ_FLUSH_LBN 0
- #define TX_DESCQ_FLUSH_WIDTH 1
-#define TX_CFG_REG_KER_OFST 0xA50 /* Transmit configuration register */
-#define TX_CFG_REG_OFST 0xA50 /* Transmit configuration register */
- #define TX_IP_ID_P1_OFS_LBN 32
- #define TX_IP_ID_P1_OFS_WIDTH 15
- #define TX_IP_ID_P0_OFS_LBN 16
- #define TX_IP_ID_P0_OFS_WIDTH 15
- #define TX_TURBO_EN_LBN 3
- #define TX_TURBO_EN_WIDTH 1
- #define TX_OWNERR_CTL_LBN 2
- #define TX_OWNERR_CTL_WIDTH 2
- #define TX_NON_IP_DROP_DIS_LBN 1
- #define TX_NON_IP_DROP_DIS_WIDTH 1
- #define TX_IP_ID_REP_EN_LBN 0
- #define TX_IP_ID_REP_EN_WIDTH 1
-#define TX_RESERVED_REG_KER_OFST 0xA80 /* Transmit configuration register */
-#define TX_RESERVED_REG_OFST 0xA80 /* Transmit configuration register */
- #define TX_CSR_PUSH_EN_LBN 89
- #define TX_CSR_PUSH_EN_WIDTH 1
- #define TX_RX_SPACER_LBN 64
- #define TX_RX_SPACER_WIDTH 8
- #define TX_SW_EV_EN_LBN 59
- #define TX_SW_EV_EN_WIDTH 1
- #define TX_RX_SPACER_EN_LBN 57
- #define TX_RX_SPACER_EN_WIDTH 1
- #define TX_CSR_PREF_WD_TMR_LBN 24
- #define TX_CSR_PREF_WD_TMR_WIDTH 16
- #define TX_CSR_ONLY1TAG_LBN 21
- #define TX_CSR_ONLY1TAG_WIDTH 1
- #define TX_PREF_THRESHOLD_LBN 19
- #define TX_PREF_THRESHOLD_WIDTH 2
- #define TX_ONE_PKT_PER_Q_LBN 18
- #define TX_ONE_PKT_PER_Q_WIDTH 1
- #define TX_DIS_NON_IP_EV_LBN 17
- #define TX_DIS_NON_IP_EV_WIDTH 1
- #define TX_DMA_SPACER_LBN 8
- #define TX_DMA_SPACER_WIDTH 8
- #define TX_FLUSH_MIN_LEN_EN_B0_LBN 7
- #define TX_FLUSH_MIN_LEN_EN_B0_WIDTH 1
- #define TX_TCP_DIS_A1_LBN 7
- #define TX_TCP_DIS_A1_WIDTH 1
- #define TX_IP_DIS_A1_LBN 6
- #define TX_IP_DIS_A1_WIDTH 1
- #define TX_MAX_CPL_LBN 2
- #define TX_MAX_CPL_WIDTH 2
- #define TX_MAX_PREF_LBN 0
- #define TX_MAX_PREF_WIDTH 2
-#define TX_VLAN_REG_OFST 0xAE0 /* Transmit VLAN tag register */
- #define TX_VLAN_EN_LBN 127
- #define TX_VLAN_EN_WIDTH 1
- #define TX_VLAN7_PORT1_EN_LBN 125
- #define TX_VLAN7_PORT1_EN_WIDTH 1
- #define TX_VLAN7_PORT0_EN_LBN 124
- #define TX_VLAN7_PORT0_EN_WIDTH 1
- #define TX_VLAN7_LBN 112
- #define TX_VLAN7_WIDTH 12
- #define TX_VLAN6_PORT1_EN_LBN 109
- #define TX_VLAN6_PORT1_EN_WIDTH 1
- #define TX_VLAN6_PORT0_EN_LBN 108
- #define TX_VLAN6_PORT0_EN_WIDTH 1
- #define TX_VLAN6_LBN 96
- #define TX_VLAN6_WIDTH 12
- #define TX_VLAN5_PORT1_EN_LBN 93
- #define TX_VLAN5_PORT1_EN_WIDTH 1
- #define TX_VLAN5_PORT0_EN_LBN 92
- #define TX_VLAN5_PORT0_EN_WIDTH 1
- #define TX_VLAN5_LBN 80
- #define TX_VLAN5_WIDTH 12
- #define TX_VLAN4_PORT1_EN_LBN 77
- #define TX_VLAN4_PORT1_EN_WIDTH 1
- #define TX_VLAN4_PORT0_EN_LBN 76
- #define TX_VLAN4_PORT0_EN_WIDTH 1
- #define TX_VLAN4_LBN 64
- #define TX_VLAN4_WIDTH 12
- #define TX_VLAN3_PORT1_EN_LBN 61
- #define TX_VLAN3_PORT1_EN_WIDTH 1
- #define TX_VLAN3_PORT0_EN_LBN 60
- #define TX_VLAN3_PORT0_EN_WIDTH 1
- #define TX_VLAN3_LBN 48
- #define TX_VLAN3_WIDTH 12
- #define TX_VLAN2_PORT1_EN_LBN 45
- #define TX_VLAN2_PORT1_EN_WIDTH 1
- #define TX_VLAN2_PORT0_EN_LBN 44
- #define TX_VLAN2_PORT0_EN_WIDTH 1
- #define TX_VLAN2_LBN 32
- #define TX_VLAN2_WIDTH 12
- #define TX_VLAN1_PORT1_EN_LBN 29
- #define TX_VLAN1_PORT1_EN_WIDTH 1
- #define TX_VLAN1_PORT0_EN_LBN 28
- #define TX_VLAN1_PORT0_EN_WIDTH 1
- #define TX_VLAN1_LBN 16
- #define TX_VLAN1_WIDTH 12
- #define TX_VLAN0_PORT1_EN_LBN 13
- #define TX_VLAN0_PORT1_EN_WIDTH 1
- #define TX_VLAN0_PORT0_EN_LBN 12
- #define TX_VLAN0_PORT0_EN_WIDTH 1
- #define TX_VLAN0_LBN 0
- #define TX_VLAN0_WIDTH 12
-#define TX_FIL_CTL_REG_OFST 0xAF0 /* Transmit filter control register */
- #define TX_MADR1_FIL_EN_LBN 65
- #define TX_MADR1_FIL_EN_WIDTH 1
- #define TX_MADR0_FIL_EN_LBN 64
- #define TX_MADR0_FIL_EN_WIDTH 1
- #define TX_IPFIL31_PORT1_EN_LBN 63
- #define TX_IPFIL31_PORT1_EN_WIDTH 1
- #define TX_IPFIL31_PORT0_EN_LBN 62
- #define TX_IPFIL31_PORT0_EN_WIDTH 1
- #define TX_IPFIL30_PORT1_EN_LBN 61
- #define TX_IPFIL30_PORT1_EN_WIDTH 1
- #define TX_IPFIL30_PORT0_EN_LBN 60
- #define TX_IPFIL30_PORT0_EN_WIDTH 1
- #define TX_IPFIL29_PORT1_EN_LBN 59
- #define TX_IPFIL29_PORT1_EN_WIDTH 1
- #define TX_IPFIL29_PORT0_EN_LBN 58
- #define TX_IPFIL29_PORT0_EN_WIDTH 1
- #define TX_IPFIL28_PORT1_EN_LBN 57
- #define TX_IPFIL28_PORT1_EN_WIDTH 1
- #define TX_IPFIL28_PORT0_EN_LBN 56
- #define TX_IPFIL28_PORT0_EN_WIDTH 1
- #define TX_IPFIL27_PORT1_EN_LBN 55
- #define TX_IPFIL27_PORT1_EN_WIDTH 1
- #define TX_IPFIL27_PORT0_EN_LBN 54
- #define TX_IPFIL27_PORT0_EN_WIDTH 1
- #define TX_IPFIL26_PORT1_EN_LBN 53
- #define TX_IPFIL26_PORT1_EN_WIDTH 1
- #define TX_IPFIL26_PORT0_EN_LBN 52
- #define TX_IPFIL26_PORT0_EN_WIDTH 1
- #define TX_IPFIL25_PORT1_EN_LBN 51
- #define TX_IPFIL25_PORT1_EN_WIDTH 1
- #define TX_IPFIL25_PORT0_EN_LBN 50
- #define TX_IPFIL25_PORT0_EN_WIDTH 1
- #define TX_IPFIL24_PORT1_EN_LBN 49
- #define TX_IPFIL24_PORT1_EN_WIDTH 1
- #define TX_IPFIL24_PORT0_EN_LBN 48
- #define TX_IPFIL24_PORT0_EN_WIDTH 1
- #define TX_IPFIL23_PORT1_EN_LBN 47
- #define TX_IPFIL23_PORT1_EN_WIDTH 1
- #define TX_IPFIL23_PORT0_EN_LBN 46
- #define TX_IPFIL23_PORT0_EN_WIDTH 1
- #define TX_IPFIL22_PORT1_EN_LBN 45
- #define TX_IPFIL22_PORT1_EN_WIDTH 1
- #define TX_IPFIL22_PORT0_EN_LBN 44
- #define TX_IPFIL22_PORT0_EN_WIDTH 1
- #define TX_IPFIL21_PORT1_EN_LBN 43
- #define TX_IPFIL21_PORT1_EN_WIDTH 1
- #define TX_IPFIL21_PORT0_EN_LBN 42
- #define TX_IPFIL21_PORT0_EN_WIDTH 1
- #define TX_IPFIL20_PORT1_EN_LBN 41
- #define TX_IPFIL20_PORT1_EN_WIDTH 1
- #define TX_IPFIL20_PORT0_EN_LBN 40
- #define TX_IPFIL20_PORT0_EN_WIDTH 1
- #define TX_IPFIL19_PORT1_EN_LBN 39
- #define TX_IPFIL19_PORT1_EN_WIDTH 1
- #define TX_IPFIL19_PORT0_EN_LBN 38
- #define TX_IPFIL19_PORT0_EN_WIDTH 1
- #define TX_IPFIL18_PORT1_EN_LBN 37
- #define TX_IPFIL18_PORT1_EN_WIDTH 1
- #define TX_IPFIL18_PORT0_EN_LBN 36
- #define TX_IPFIL18_PORT0_EN_WIDTH 1
- #define TX_IPFIL17_PORT1_EN_LBN 35
- #define TX_IPFIL17_PORT1_EN_WIDTH 1
- #define TX_IPFIL17_PORT0_EN_LBN 34
- #define TX_IPFIL17_PORT0_EN_WIDTH 1
- #define TX_IPFIL16_PORT1_EN_LBN 33
- #define TX_IPFIL16_PORT1_EN_WIDTH 1
- #define TX_IPFIL16_PORT0_EN_LBN 32
- #define TX_IPFIL16_PORT0_EN_WIDTH 1
- #define TX_IPFIL15_PORT1_EN_LBN 31
- #define TX_IPFIL15_PORT1_EN_WIDTH 1
- #define TX_IPFIL15_PORT0_EN_LBN 30
- #define TX_IPFIL15_PORT0_EN_WIDTH 1
- #define TX_IPFIL14_PORT1_EN_LBN 29
- #define TX_IPFIL14_PORT1_EN_WIDTH 1
- #define TX_IPFIL14_PORT0_EN_LBN 28
- #define TX_IPFIL14_PORT0_EN_WIDTH 1
- #define TX_IPFIL13_PORT1_EN_LBN 27
- #define TX_IPFIL13_PORT1_EN_WIDTH 1
- #define TX_IPFIL13_PORT0_EN_LBN 26
- #define TX_IPFIL13_PORT0_EN_WIDTH 1
- #define TX_IPFIL12_PORT1_EN_LBN 25
- #define TX_IPFIL12_PORT1_EN_WIDTH 1
- #define TX_IPFIL12_PORT0_EN_LBN 24
- #define TX_IPFIL12_PORT0_EN_WIDTH 1
- #define TX_IPFIL11_PORT1_EN_LBN 23
- #define TX_IPFIL11_PORT1_EN_WIDTH 1
- #define TX_IPFIL11_PORT0_EN_LBN 22
- #define TX_IPFIL11_PORT0_EN_WIDTH 1
- #define TX_IPFIL10_PORT1_EN_LBN 21
- #define TX_IPFIL10_PORT1_EN_WIDTH 1
- #define TX_IPFIL10_PORT0_EN_LBN 20
- #define TX_IPFIL10_PORT0_EN_WIDTH 1
- #define TX_IPFIL9_PORT1_EN_LBN 19
- #define TX_IPFIL9_PORT1_EN_WIDTH 1
- #define TX_IPFIL9_PORT0_EN_LBN 18
- #define TX_IPFIL9_PORT0_EN_WIDTH 1
- #define TX_IPFIL8_PORT1_EN_LBN 17
- #define TX_IPFIL8_PORT1_EN_WIDTH 1
- #define TX_IPFIL8_PORT0_EN_LBN 16
- #define TX_IPFIL8_PORT0_EN_WIDTH 1
- #define TX_IPFIL7_PORT1_EN_LBN 15
- #define TX_IPFIL7_PORT1_EN_WIDTH 1
- #define TX_IPFIL7_PORT0_EN_LBN 14
- #define TX_IPFIL7_PORT0_EN_WIDTH 1
- #define TX_IPFIL6_PORT1_EN_LBN 13
- #define TX_IPFIL6_PORT1_EN_WIDTH 1
- #define TX_IPFIL6_PORT0_EN_LBN 12
- #define TX_IPFIL6_PORT0_EN_WIDTH 1
- #define TX_IPFIL5_PORT1_EN_LBN 11
- #define TX_IPFIL5_PORT1_EN_WIDTH 1
- #define TX_IPFIL5_PORT0_EN_LBN 10
- #define TX_IPFIL5_PORT0_EN_WIDTH 1
- #define TX_IPFIL4_PORT1_EN_LBN 9
- #define TX_IPFIL4_PORT1_EN_WIDTH 1
- #define TX_IPFIL4_PORT0_EN_LBN 8
- #define TX_IPFIL4_PORT0_EN_WIDTH 1
- #define TX_IPFIL3_PORT1_EN_LBN 7
- #define TX_IPFIL3_PORT1_EN_WIDTH 1
- #define TX_IPFIL3_PORT0_EN_LBN 6
- #define TX_IPFIL3_PORT0_EN_WIDTH 1
- #define TX_IPFIL2_PORT1_EN_LBN 5
- #define TX_IPFIL2_PORT1_EN_WIDTH 1
- #define TX_IPFIL2_PORT0_EN_LBN 4
- #define TX_IPFIL2_PORT0_EN_WIDTH 1
- #define TX_IPFIL1_PORT1_EN_LBN 3
- #define TX_IPFIL1_PORT1_EN_WIDTH 1
- #define TX_IPFIL1_PORT0_EN_LBN 2
- #define TX_IPFIL1_PORT0_EN_WIDTH 1
- #define TX_IPFIL0_PORT1_EN_LBN 1
- #define TX_IPFIL0_PORT1_EN_WIDTH 1
- #define TX_IPFIL0_PORT0_EN_LBN 0
- #define TX_IPFIL0_PORT0_EN_WIDTH 1
-#define TX_IPFIL_TBL_OFST 0xB00 /* Transmit IP source address filter table */
- #define TX_IPFIL_MASK_LBN 32
- #define TX_IPFIL_MASK_WIDTH 32
- #define TX_IP_SRC_ADR_LBN 0
- #define TX_IP_SRC_ADR_WIDTH 32
-#define TX_PACE_REG_A1_OFST 0xF80000 /* Transmit pace control register */
-#define TX_PACE_REG_B0_OFST 0xA90 /* Transmit pace control register */
- #define TX_PACE_SB_AF_LBN 19
- #define TX_PACE_SB_AF_WIDTH 10
- #define TX_PACE_SB_NOTAF_LBN 9
- #define TX_PACE_SB_NOTAF_WIDTH 10
- #define TX_PACE_FB_BASE_LBN 5
- #define TX_PACE_FB_BASE_WIDTH 4
- #define TX_PACE_BIN_TH_LBN 0
- #define TX_PACE_BIN_TH_WIDTH 5
-#define TX_PACE_TBL_A1_OFST 0xF80040 /* Transmit pacing table */
-#define TX_PACE_TBL_FIRST_QUEUE_A1 4
-#define TX_PACE_TBL_B0_OFST 0xF80000 /* Transmit pacing table */
-#define TX_PACE_TBL_FIRST_QUEUE_B0 0
- #define TX_PACE_LBN 0
- #define TX_PACE_WIDTH 5
-
-/*************---- EE/Flash Registers C Header ----*************/
-#define EE_SPI_HCMD_REG_KER_OFST 0x100 /* SPI host command register */
-#define EE_SPI_HCMD_REG_OFST 0x100 /* SPI host command register */
- #define EE_SPI_HCMD_CMD_EN_LBN 31
- #define EE_SPI_HCMD_CMD_EN_WIDTH 1
- #define EE_WR_TIMER_ACTIVE_LBN 28
- #define EE_WR_TIMER_ACTIVE_WIDTH 1
- #define EE_SPI_HCMD_SF_SEL_LBN 24
- #define EE_SPI_HCMD_SF_SEL_WIDTH 1
- #define EE_SPI_HCMD_DABCNT_LBN 16
- #define EE_SPI_HCMD_DABCNT_WIDTH 5
- #define EE_SPI_HCMD_READ_LBN 15
- #define EE_SPI_HCMD_READ_WIDTH 1
- #define EE_SPI_HCMD_DUBCNT_LBN 12
- #define EE_SPI_HCMD_DUBCNT_WIDTH 2
- #define EE_SPI_HCMD_ADBCNT_LBN 8
- #define EE_SPI_HCMD_ADBCNT_WIDTH 2
- #define EE_SPI_HCMD_ENC_LBN 0
- #define EE_SPI_HCMD_ENC_WIDTH 8
-#define EE_SPI_HADR_REG_KER_OFST 0X110 /* SPI host address register */
-#define EE_SPI_HADR_REG_OFST 0X110 /* SPI host address register */
- #define EE_SPI_HADR_DUBYTE_LBN 24
- #define EE_SPI_HADR_DUBYTE_WIDTH 8
- #define EE_SPI_HADR_ADR_LBN 0
- #define EE_SPI_HADR_ADR_WIDTH 24
-#define EE_SPI_HDATA_REG_KER_OFST 0x120 /* SPI host data register */
-#define EE_SPI_HDATA_REG_OFST 0x120 /* SPI host data register */
- #define EE_SPI_HDATA3_LBN 96
- #define EE_SPI_HDATA3_WIDTH 32
- #define EE_SPI_HDATA2_LBN 64
- #define EE_SPI_HDATA2_WIDTH 32
- #define EE_SPI_HDATA1_LBN 32
- #define EE_SPI_HDATA1_WIDTH 32
- #define EE_SPI_HDATA0_LBN 0
- #define EE_SPI_HDATA0_WIDTH 32
-#define EE_BASE_PAGE_REG_KER_OFST 0x130 /* Expansion ROM base mirror register
*/
-#define EE_BASE_PAGE_REG_OFST 0x130 /* Expansion ROM base mirror register */
- #define EE_EXP_ROM_WINDOW_BASE_LBN 16
- #define EE_EXP_ROM_WINDOW_BASE_WIDTH 13
- #define EE_EXPROM_MASK_LBN 0
- #define EE_EXPROM_MASK_WIDTH 13
-#define EE_VPD_CFG0_REG_KER_OFST 0X140 /* SPI/VPD configuration register */
-#define EE_VPD_CFG0_REG_OFST 0X140 /* SPI/VPD configuration register */
- #define EE_SF_FASTRD_EN_LBN 127
- #define EE_SF_FASTRD_EN_WIDTH 1
- #define EE_SF_CLOCK_DIV_LBN 120
- #define EE_SF_CLOCK_DIV_WIDTH 7
- #define EE_VPD_WIP_POLL_LBN 119
- #define EE_VPD_WIP_POLL_WIDTH 1
- #define EE_VPDW_LENGTH_LBN 80
- #define EE_VPDW_LENGTH_WIDTH 15
- #define EE_VPDW_BASE_LBN 64
- #define EE_VPDW_BASE_WIDTH 15
- #define EE_VPD_WR_CMD_EN_LBN 56
- #define EE_VPD_WR_CMD_EN_WIDTH 8
- #define EE_VPD_BASE_LBN 32
- #define EE_VPD_BASE_WIDTH 24
- #define EE_VPD_LENGTH_LBN 16
- #define EE_VPD_LENGTH_WIDTH 13
- #define EE_VPD_AD_SIZE_LBN 8
- #define EE_VPD_AD_SIZE_WIDTH 5
- #define EE_VPD_ACCESS_ON_LBN 5
- #define EE_VPD_ACCESS_ON_WIDTH 1
-#define EE_VPD_SW_CNTL_REG_KER_OFST 0X150 /* VPD access SW control register */
-#define EE_VPD_SW_CNTL_REG_OFST 0X150 /* VPD access SW control register */
- #define EE_VPD_CYCLE_PENDING_LBN 31
- #define EE_VPD_CYCLE_PENDING_WIDTH 1
- #define EE_VPD_CYC_WRITE_LBN 28
- #define EE_VPD_CYC_WRITE_WIDTH 1
- #define EE_VPD_CYC_ADR_LBN 0
- #define EE_VPD_CYC_ADR_WIDTH 15
-#define EE_VPD_SW_DATA_REG_KER_OFST 0x160 /* VPD access SW data register */
-#define EE_VPD_SW_DATA_REG_OFST 0x160 /* VPD access SW data register */
- #define EE_VPD_CYC_DAT_LBN 0
- #define EE_VPD_CYC_DAT_WIDTH 32
diff -r 0b5ca7cdbdfc -r b8c2a9aacba6
drivers/net/sfc/sfc_resource/ci/driver/efab/hardware/falcon/falcon_desc.h
--- a/drivers/net/sfc/sfc_resource/ci/driver/efab/hardware/falcon/falcon_desc.h
Fri Jan 08 13:05:49 2010 +0000
+++ b/drivers/net/sfc/sfc_resource/ci/driver/efab/hardware/falcon/falcon_desc.h
Fri Jan 08 13:06:22 2010 +0000
@@ -6,7 +6,7 @@
* This file provides EtherFabric NIC - EFXXXX (aka Falcon) descriptor
* definitions.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
diff -r 0b5ca7cdbdfc -r b8c2a9aacba6
drivers/net/sfc/sfc_resource/ci/driver/efab/hardware/falcon/falcon_event.h
---
a/drivers/net/sfc/sfc_resource/ci/driver/efab/hardware/falcon/falcon_event.h
Fri Jan 08 13:05:49 2010 +0000
+++
b/drivers/net/sfc/sfc_resource/ci/driver/efab/hardware/falcon/falcon_event.h
Fri Jan 08 13:06:22 2010 +0000
@@ -6,7 +6,7 @@
* This file provides EtherFabric NIC - EFXXXX (aka Falcon) event
* definitions.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
@@ -126,6 +126,8 @@
#define TX_PKT_NON_TCP_UDP_DECODE 0x9
#define TIMER_EV_DECODE 0xA
#define RX_DSC_ERROR_EV_DECODE 0xE
+ #define DRIVER_EV_RX_FLUSH_FAIL_LBN 12
+ #define DRIVER_EV_RX_FLUSH_FAIL_WIDTH 1
#define DRIVER_EV_TX_DESCQ_ID_LBN 0
#define DRIVER_EV_TX_DESCQ_ID_WIDTH 12
#define DRIVER_EV_RX_DESCQ_ID_LBN 0
diff -r 0b5ca7cdbdfc -r b8c2a9aacba6
drivers/net/sfc/sfc_resource/ci/driver/efab/hardware/falcon/falcon_grmon.h
---
a/drivers/net/sfc/sfc_resource/ci/driver/efab/hardware/falcon/falcon_grmon.h
Fri Jan 08 13:05:49 2010 +0000
+++
b/drivers/net/sfc/sfc_resource/ci/driver/efab/hardware/falcon/falcon_grmon.h
Fri Jan 08 13:06:22 2010 +0000
@@ -6,7 +6,7 @@
* This file provides EtherFabric NIC - EFXXXX (aka Falcon) 1G MAC
* counters.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
diff -r 0b5ca7cdbdfc -r b8c2a9aacba6
drivers/net/sfc/sfc_resource/ci/driver/efab/hardware/falcon/falcon_intr_vec.h
---
a/drivers/net/sfc/sfc_resource/ci/driver/efab/hardware/falcon/falcon_intr_vec.h
Fri Jan 08 13:05:49 2010 +0000
+++
b/drivers/net/sfc/sfc_resource/ci/driver/efab/hardware/falcon/falcon_intr_vec.h
Fri Jan 08 13:06:22 2010 +0000
@@ -6,7 +6,7 @@
* This file provides EtherFabric NIC - EFXXXX (aka Falcon) interrupt
* vector definitions.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
diff -r 0b5ca7cdbdfc -r b8c2a9aacba6
drivers/net/sfc/sfc_resource/ci/driver/efab/hardware/falcon/falcon_mac.h
--- a/drivers/net/sfc/sfc_resource/ci/driver/efab/hardware/falcon/falcon_mac.h
Fri Jan 08 13:05:49 2010 +0000
+++ b/drivers/net/sfc/sfc_resource/ci/driver/efab/hardware/falcon/falcon_mac.h
Fri Jan 08 13:06:22 2010 +0000
@@ -6,7 +6,7 @@
* This file provides EtherFabric NIC - EFXXXX (aka Falcon) MAC register
* definitions.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
@@ -29,6 +29,7 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
****************************************************************************
*/
+#ifdef USE_OLD_HWDEFS
/*********---- 1G/10G Ethernet MAC Wrapper Registers C Header ----*********/
#define MD_TXD_REG_KER_OFST 0xC00 /* PHY management transmit data register */
@@ -709,3 +710,4 @@
#define XX_DISPERR_CH1_WIDTH 1
#define XX_DISPERR_CH0_LBN 0
#define XX_DISPERR_CH0_WIDTH 1
+#endif
diff -r 0b5ca7cdbdfc -r b8c2a9aacba6
drivers/net/sfc/sfc_resource/ci/driver/efab/hardware/falcon/falcon_xgrmon.h
---
a/drivers/net/sfc/sfc_resource/ci/driver/efab/hardware/falcon/falcon_xgrmon.h
Fri Jan 08 13:05:49 2010 +0000
+++
b/drivers/net/sfc/sfc_resource/ci/driver/efab/hardware/falcon/falcon_xgrmon.h
Fri Jan 08 13:06:22 2010 +0000
@@ -6,7 +6,7 @@
* This file provides EtherFabric NIC - EFXXXX (aka Falcon) 10G MAC
* statistics register definitions.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
diff -r 0b5ca7cdbdfc -r b8c2a9aacba6
drivers/net/sfc/sfc_resource/ci/driver/efab/hardware/host_common.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/net/sfc/sfc_resource/ci/driver/efab/hardware/host_common.h
Fri Jan 08 13:06:22 2010 +0000
@@ -0,0 +1,2850 @@
+/****************************************************************************
+ * Driver for Solarflare network controllers -
+ * resource management for Xen backend, OpenOnload, etc
+ * (including support for SFE4001 10GBT NIC)
+ *
+ * This file provides EtherFabric NIC hardware interface common
+ * definitions.
+ *
+ * Copyright 2005-2010: Solarflare Communications Inc,
+ * 9501 Jeronimo Road, Suite 250,
+ * Irvine, CA 92618, USA
+ *
+ * Developed and maintained by Solarflare Communications:
+ * <linux-xen-drivers@xxxxxxxxxxxxxx>
+ * <onload-dev@xxxxxxxxxxxxxx>
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation, incorporated herein by reference.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ ****************************************************************************
+ */
+
+#ifndef HOST_PROGMODEL_DEFS_H
+#define HOST_PROGMODEL_DEFS_H
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_IOM_IND_ADR_REG(32bit):
+ * IO-mapped indirect access address register
+ */
+#define FR_AZ_IOM_IND_ADR_REG_OFST 0x00000000
+/* falcona0,falconb0,sienaa0=net_func_bar0 */
+
+#define FRF_AZ_IOM_AUTO_ADR_INC_EN_LBN 24
+#define FRF_AZ_IOM_AUTO_ADR_INC_EN_WIDTH 1
+#define FRF_AZ_IOM_IND_ADR_LBN 0
+#define FRF_AZ_IOM_IND_ADR_WIDTH 24
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_IOM_IND_DAT_REG(32bit):
+ * IO-mapped indirect access data register
+ */
+#define FR_AZ_IOM_IND_DAT_REG_OFST 0x00000004
+/* falcona0,falconb0,sienaa0=net_func_bar0 */
+
+#define FRF_AZ_IOM_IND_DAT_LBN 0
+#define FRF_AZ_IOM_IND_DAT_WIDTH 32
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_ADR_REGION_REG(128bit):
+ * Address region register
+ */
+#define FR_AZ_ADR_REGION_REG_OFST 0x00000000
+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AZ_ADR_REGION3_LBN 96
+#define FRF_AZ_ADR_REGION3_WIDTH 18
+#define FRF_AZ_ADR_REGION2_LBN 64
+#define FRF_AZ_ADR_REGION2_WIDTH 18
+#define FRF_AZ_ADR_REGION1_LBN 32
+#define FRF_AZ_ADR_REGION1_WIDTH 18
+#define FRF_AZ_ADR_REGION0_LBN 0
+#define FRF_AZ_ADR_REGION0_WIDTH 18
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_INT_EN_REG_KER(128bit):
+ * Kernel driver Interrupt enable register
+ */
+#define FR_AZ_INT_EN_REG_KER_OFST 0x00000010
+/* falcona0,falconb0,sienaa0=net_func_bar2 */
+
+#define FRF_AZ_KER_INT_LEVE_SEL_LBN 8
+#define FRF_AZ_KER_INT_LEVE_SEL_WIDTH 6
+#define FRF_AZ_KER_INT_CHAR_LBN 4
+#define FRF_AZ_KER_INT_CHAR_WIDTH 1
+#define FRF_AZ_KER_INT_KER_LBN 3
+#define FRF_AZ_KER_INT_KER_WIDTH 1
+#define FRF_AZ_DRV_INT_EN_KER_LBN 0
+#define FRF_AZ_DRV_INT_EN_KER_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_INT_EN_REG_CHAR(128bit):
+ * Char Driver interrupt enable register
+ */
+#define FR_AZ_INT_EN_REG_CHAR_OFST 0x00000020
+/* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AZ_CHAR_INT_LEVE_SEL_LBN 8
+#define FRF_AZ_CHAR_INT_LEVE_SEL_WIDTH 6
+#define FRF_AZ_CHAR_INT_CHAR_LBN 4
+#define FRF_AZ_CHAR_INT_CHAR_WIDTH 1
+#define FRF_AZ_CHAR_INT_KER_LBN 3
+#define FRF_AZ_CHAR_INT_KER_WIDTH 1
+#define FRF_AZ_DRV_INT_EN_CHAR_LBN 0
+#define FRF_AZ_DRV_INT_EN_CHAR_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_INT_ADR_REG_KER(128bit):
+ * Interrupt host address for Kernel driver
+ */
+#define FR_AZ_INT_ADR_REG_KER_OFST 0x00000030
+/* falcona0,falconb0,sienaa0=net_func_bar2 */
+
+#define FRF_AZ_NORM_INT_VEC_DIS_KER_LBN 64
+#define FRF_AZ_NORM_INT_VEC_DIS_KER_WIDTH 1
+#define FRF_AZ_INT_ADR_KER_LBN 0
+#define FRF_AZ_INT_ADR_KER_WIDTH 64
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_INT_ADR_REG_CHAR(128bit):
+ * Interrupt host address for Char driver
+ */
+#define FR_AZ_INT_ADR_REG_CHAR_OFST 0x00000040
+/* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AZ_NORM_INT_VEC_DIS_CHAR_LBN 64
+#define FRF_AZ_NORM_INT_VEC_DIS_CHAR_WIDTH 1
+#define FRF_AZ_INT_ADR_CHAR_LBN 0
+#define FRF_AZ_INT_ADR_CHAR_WIDTH 64
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AA_INT_ACK_KER(32bit):
+ * Kernel interrupt acknowledge register
+ */
+#define FR_AA_INT_ACK_KER_OFST 0x00000050
+/* falcona0=net_func_bar2 */
+
+#define FRF_AA_INT_ACK_KER_FIELD_LBN 0
+#define FRF_AA_INT_ACK_KER_FIELD_WIDTH 32
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_BZ_INT_ISR0_REG(128bit):
+ * Function 0 Interrupt Acknowlege Status register
+ */
+#define FR_BZ_INT_ISR0_REG_OFST 0x00000090
+/* falconb0,sienaa0=net_func_bar2 */
+
+#define FRF_BZ_INT_ISR_REG_LBN 0
+#define FRF_BZ_INT_ISR_REG_WIDTH 64
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_HW_INIT_REG(128bit):
+ * Hardware initialization register
+ */
+#define FR_AZ_HW_INIT_REG_OFST 0x000000c0
+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_BB_BDMRD_CPLF_FULL_LBN 124
+#define FRF_BB_BDMRD_CPLF_FULL_WIDTH 1
+#define FRF_BB_PCIE_CPL_TIMEOUT_CTRL_LBN 121
+#define FRF_BB_PCIE_CPL_TIMEOUT_CTRL_WIDTH 3
+#define FRF_CZ_TX_MRG_TAGS_LBN 120
+#define FRF_CZ_TX_MRG_TAGS_WIDTH 1
+#define FRF_AB_TRGT_MASK_ALL_LBN 100
+#define FRF_AB_TRGT_MASK_ALL_WIDTH 1
+#define FRF_AZ_DOORBELL_DROP_LBN 92
+#define FRF_AZ_DOORBELL_DROP_WIDTH 8
+#define FRF_AB_TX_RREQ_MASK_EN_LBN 76
+#define FRF_AB_TX_RREQ_MASK_EN_WIDTH 1
+#define FRF_AB_PE_EIDLE_DIS_LBN 75
+#define FRF_AB_PE_EIDLE_DIS_WIDTH 1
+#define FRF_AA_FC_BLOCKING_EN_LBN 45
+#define FRF_AA_FC_BLOCKING_EN_WIDTH 1
+#define FRF_BZ_B2B_REQ_EN_LBN 45
+#define FRF_BZ_B2B_REQ_EN_WIDTH 1
+#define FRF_AA_B2B_REQ_EN_LBN 44
+#define FRF_AA_B2B_REQ_EN_WIDTH 1
+#define FRF_BB_FC_BLOCKING_EN_LBN 44
+#define FRF_BB_FC_BLOCKING_EN_WIDTH 1
+#define FRF_AZ_POST_WR_MASK_LBN 40
+#define FRF_AZ_POST_WR_MASK_WIDTH 4
+#define FRF_AZ_TLP_TC_LBN 34
+#define FRF_AZ_TLP_TC_WIDTH 3
+#define FRF_AZ_TLP_ATTR_LBN 32
+#define FRF_AZ_TLP_ATTR_WIDTH 2
+#define FRF_AB_INTB_VEC_LBN 24
+#define FRF_AB_INTB_VEC_WIDTH 5
+#define FRF_AB_INTA_VEC_LBN 16
+#define FRF_AB_INTA_VEC_WIDTH 5
+#define FRF_AZ_WD_TIMER_LBN 8
+#define FRF_AZ_WD_TIMER_WIDTH 8
+#define FRF_AZ_US_DISABLE_LBN 5
+#define FRF_AZ_US_DISABLE_WIDTH 1
+#define FRF_AZ_TLP_EP_LBN 4
+#define FRF_AZ_TLP_EP_WIDTH 1
+#define FRF_AZ_ATTR_SEL_LBN 3
+#define FRF_AZ_ATTR_SEL_WIDTH 1
+#define FRF_AZ_TD_SEL_LBN 1
+#define FRF_AZ_TD_SEL_WIDTH 1
+#define FRF_AZ_TLP_TD_LBN 0
+#define FRF_AZ_TLP_TD_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_EE_SPI_HCMD_REG(128bit):
+ * SPI host command register
+ */
+#define FR_AB_EE_SPI_HCMD_REG_OFST 0x00000100
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_EE_SPI_HCMD_CMD_EN_LBN 31
+#define FRF_AB_EE_SPI_HCMD_CMD_EN_WIDTH 1
+#define FRF_AB_EE_WR_TIMER_ACTIVE_LBN 28
+#define FRF_AB_EE_WR_TIMER_ACTIVE_WIDTH 1
+#define FRF_AB_EE_SPI_HCMD_SF_SEL_LBN 24
+#define FRF_AB_EE_SPI_HCMD_SF_SEL_WIDTH 1
+#define FRF_AB_EE_SPI_HCMD_DABCNT_LBN 16
+#define FRF_AB_EE_SPI_HCMD_DABCNT_WIDTH 5
+#define FRF_AB_EE_SPI_HCMD_READ_LBN 15
+#define FRF_AB_EE_SPI_HCMD_READ_WIDTH 1
+#define FRF_AB_EE_SPI_HCMD_DUBCNT_LBN 12
+#define FRF_AB_EE_SPI_HCMD_DUBCNT_WIDTH 2
+#define FRF_AB_EE_SPI_HCMD_ADBCNT_LBN 8
+#define FRF_AB_EE_SPI_HCMD_ADBCNT_WIDTH 2
+#define FRF_AB_EE_SPI_HCMD_ENC_LBN 0
+#define FRF_AB_EE_SPI_HCMD_ENC_WIDTH 8
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_CZ_USR_EV_CFG(128bit):
+ * User Level Event Configuration register
+ */
+#define FR_CZ_USR_EV_CFG_OFST 0x00000100
+/* sienaa0=net_func_bar2 */
+
+#define FRF_CZ_USREV_DIS_LBN 16
+#define FRF_CZ_USREV_DIS_WIDTH 1
+#define FRF_CZ_DFLT_EVQ_LBN 0
+#define FRF_CZ_DFLT_EVQ_WIDTH 10
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_EE_SPI_HADR_REG(128bit):
+ * SPI host address register
+ */
+#define FR_AB_EE_SPI_HADR_REG_OFST 0x00000110
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_EE_SPI_HADR_DUBYTE_LBN 24
+#define FRF_AB_EE_SPI_HADR_DUBYTE_WIDTH 8
+#define FRF_AB_EE_SPI_HADR_ADR_LBN 0
+#define FRF_AB_EE_SPI_HADR_ADR_WIDTH 24
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_EE_SPI_HDATA_REG(128bit):
+ * SPI host data register
+ */
+#define FR_AB_EE_SPI_HDATA_REG_OFST 0x00000120
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_EE_SPI_HDATA3_LBN 96
+#define FRF_AB_EE_SPI_HDATA3_WIDTH 32
+#define FRF_AB_EE_SPI_HDATA2_LBN 64
+#define FRF_AB_EE_SPI_HDATA2_WIDTH 32
+#define FRF_AB_EE_SPI_HDATA1_LBN 32
+#define FRF_AB_EE_SPI_HDATA1_WIDTH 32
+#define FRF_AB_EE_SPI_HDATA0_LBN 0
+#define FRF_AB_EE_SPI_HDATA0_WIDTH 32
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_EE_BASE_PAGE_REG(128bit):
+ * Expansion ROM base mirror register
+ */
+#define FR_AB_EE_BASE_PAGE_REG_OFST 0x00000130
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_EE_EXPROM_MASK_LBN 16
+#define FRF_AB_EE_EXPROM_MASK_WIDTH 13
+#define FRF_AB_EE_EXP_ROM_WINDOW_BASE_LBN 0
+#define FRF_AB_EE_EXP_ROM_WINDOW_BASE_WIDTH 13
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_EE_VPD_CFG0_REG(128bit):
+ * SPI/VPD configuration register 0
+ */
+#define FR_AB_EE_VPD_CFG0_REG_OFST 0x00000140
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_EE_SF_FASTRD_EN_LBN 127
+#define FRF_AB_EE_SF_FASTRD_EN_WIDTH 1
+#define FRF_AB_EE_SF_CLOCK_DIV_LBN 120
+#define FRF_AB_EE_SF_CLOCK_DIV_WIDTH 7
+#define FRF_AB_EE_VPD_WIP_POLL_LBN 119
+#define FRF_AB_EE_VPD_WIP_POLL_WIDTH 1
+#define FRF_AB_EE_EE_CLOCK_DIV_LBN 112
+#define FRF_AB_EE_EE_CLOCK_DIV_WIDTH 7
+#define FRF_AB_EE_EE_WR_TMR_VALUE_LBN 96
+#define FRF_AB_EE_EE_WR_TMR_VALUE_WIDTH 16
+#define FRF_AB_EE_VPDW_LENGTH_LBN 80
+#define FRF_AB_EE_VPDW_LENGTH_WIDTH 15
+#define FRF_AB_EE_VPDW_BASE_LBN 64
+#define FRF_AB_EE_VPDW_BASE_WIDTH 15
+#define FRF_AB_EE_VPD_WR_CMD_EN_LBN 56
+#define FRF_AB_EE_VPD_WR_CMD_EN_WIDTH 8
+#define FRF_AB_EE_VPD_BASE_LBN 32
+#define FRF_AB_EE_VPD_BASE_WIDTH 24
+#define FRF_AB_EE_VPD_LENGTH_LBN 16
+#define FRF_AB_EE_VPD_LENGTH_WIDTH 15
+#define FRF_AB_EE_VPD_AD_SIZE_LBN 8
+#define FRF_AB_EE_VPD_AD_SIZE_WIDTH 5
+#define FRF_AB_EE_VPD_ACCESS_ON_LBN 5
+#define FRF_AB_EE_VPD_ACCESS_ON_WIDTH 1
+#define FRF_AB_EE_VPD_ACCESS_BLOCK_LBN 4
+#define FRF_AB_EE_VPD_ACCESS_BLOCK_WIDTH 1
+#define FRF_AB_EE_VPD_DEV_SF_SEL_LBN 2
+#define FRF_AB_EE_VPD_DEV_SF_SEL_WIDTH 1
+#define FRF_AB_EE_VPD_EN_AD9_MODE_LBN 1
+#define FRF_AB_EE_VPD_EN_AD9_MODE_WIDTH 1
+#define FRF_AB_EE_VPD_EN_LBN 0
+#define FRF_AB_EE_VPD_EN_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_EE_VPD_SW_CNTL_REG(128bit):
+ * VPD access SW control register
+ */
+#define FR_AB_EE_VPD_SW_CNTL_REG_OFST 0x00000150
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_EE_VPD_CYCLE_PENDING_LBN 31
+#define FRF_AB_EE_VPD_CYCLE_PENDING_WIDTH 1
+#define FRF_AB_EE_VPD_CYC_WRITE_LBN 28
+#define FRF_AB_EE_VPD_CYC_WRITE_WIDTH 1
+#define FRF_AB_EE_VPD_CYC_ADR_LBN 0
+#define FRF_AB_EE_VPD_CYC_ADR_WIDTH 15
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_EE_VPD_SW_DATA_REG(128bit):
+ * VPD access SW data register
+ */
+#define FR_AB_EE_VPD_SW_DATA_REG_OFST 0x00000160
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_EE_VPD_CYC_DAT_LBN 0
+#define FRF_AB_EE_VPD_CYC_DAT_WIDTH 32
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_BB_PCIE_CORE_INDIRECT_REG(64bit):
+ * Indirect Access to PCIE Core registers
+ */
+#define FR_BB_PCIE_CORE_INDIRECT_REG_OFST 0x000001f0
+/* falconb0=net_func_bar2 */
+
+#define FRF_BB_PCIE_CORE_TARGET_DATA_LBN 32
+#define FRF_BB_PCIE_CORE_TARGET_DATA_WIDTH 32
+#define FRF_BB_PCIE_CORE_INDIRECT_ACCESS_DIR_LBN 15
+#define FRF_BB_PCIE_CORE_INDIRECT_ACCESS_DIR_WIDTH 1
+#define FRF_BB_PCIE_CORE_TARGET_REG_ADRS_LBN 0
+#define FRF_BB_PCIE_CORE_TARGET_REG_ADRS_WIDTH 12
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_NIC_STAT_REG(128bit):
+ * NIC status register
+ */
+#define FR_AB_NIC_STAT_REG_OFST 0x00000200
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_BB_AER_DIS_LBN 34
+#define FRF_BB_AER_DIS_WIDTH 1
+#define FRF_BB_EE_STRAP_EN_LBN 31
+#define FRF_BB_EE_STRAP_EN_WIDTH 1
+#define FRF_BB_EE_STRAP_LBN 24
+#define FRF_BB_EE_STRAP_WIDTH 4
+#define FRF_BB_REVISION_ID_LBN 17
+#define FRF_BB_REVISION_ID_WIDTH 7
+#define FRF_AB_ONCHIP_SRAM_LBN 16
+#define FRF_AB_ONCHIP_SRAM_WIDTH 1
+#define FRF_AB_SF_PRST_LBN 9
+#define FRF_AB_SF_PRST_WIDTH 1
+#define FRF_AB_EE_PRST_LBN 8
+#define FRF_AB_EE_PRST_WIDTH 1
+#define FRF_AB_ATE_MODE_LBN 3
+#define FRF_AB_ATE_MODE_WIDTH 1
+#define FRF_AB_STRAP_PINS_LBN 0
+#define FRF_AB_STRAP_PINS_WIDTH 3
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_GPIO_CTL_REG(128bit):
+ * GPIO control register
+ */
+#define FR_AB_GPIO_CTL_REG_OFST 0x00000210
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_GPIO_OUT3_LBN 112
+#define FRF_AB_GPIO_OUT3_WIDTH 16
+#define FRF_AB_GPIO_IN3_LBN 104
+#define FRF_AB_GPIO_IN3_WIDTH 8
+#define FRF_AB_GPIO_PWRUP_VALUE3_LBN 96
+#define FRF_AB_GPIO_PWRUP_VALUE3_WIDTH 8
+#define FRF_AB_GPIO_OUT2_LBN 80
+#define FRF_AB_GPIO_OUT2_WIDTH 16
+#define FRF_AB_GPIO_IN2_LBN 72
+#define FRF_AB_GPIO_IN2_WIDTH 8
+#define FRF_AB_GPIO_PWRUP_VALUE2_LBN 64
+#define FRF_AB_GPIO_PWRUP_VALUE2_WIDTH 8
+#define FRF_AB_GPIO15_OEN_LBN 63
+#define FRF_AB_GPIO15_OEN_WIDTH 1
+#define FRF_AB_GPIO14_OEN_LBN 62
+#define FRF_AB_GPIO14_OEN_WIDTH 1
+#define FRF_AB_GPIO13_OEN_LBN 61
+#define FRF_AB_GPIO13_OEN_WIDTH 1
+#define FRF_AB_GPIO12_OEN_LBN 60
+#define FRF_AB_GPIO12_OEN_WIDTH 1
+#define FRF_AB_GPIO11_OEN_LBN 59
+#define FRF_AB_GPIO11_OEN_WIDTH 1
+#define FRF_AB_GPIO10_OEN_LBN 58
+#define FRF_AB_GPIO10_OEN_WIDTH 1
+#define FRF_AB_GPIO9_OEN_LBN 57
+#define FRF_AB_GPIO9_OEN_WIDTH 1
+#define FRF_AB_GPIO8_OEN_LBN 56
+#define FRF_AB_GPIO8_OEN_WIDTH 1
+#define FRF_AB_GPIO15_OUT_LBN 55
+#define FRF_AB_GPIO15_OUT_WIDTH 1
+#define FRF_AB_GPIO14_OUT_LBN 54
+#define FRF_AB_GPIO14_OUT_WIDTH 1
+#define FRF_AB_GPIO13_OUT_LBN 53
+#define FRF_AB_GPIO13_OUT_WIDTH 1
+#define FRF_AB_GPIO12_OUT_LBN 52
+#define FRF_AB_GPIO12_OUT_WIDTH 1
+#define FRF_AB_GPIO11_OUT_LBN 51
+#define FRF_AB_GPIO11_OUT_WIDTH 1
+#define FRF_AB_GPIO10_OUT_LBN 50
+#define FRF_AB_GPIO10_OUT_WIDTH 1
+#define FRF_AB_GPIO9_OUT_LBN 49
+#define FRF_AB_GPIO9_OUT_WIDTH 1
+#define FRF_AB_GPIO8_OUT_LBN 48
+#define FRF_AB_GPIO8_OUT_WIDTH 1
+#define FRF_AB_GPIO15_IN_LBN 47
+#define FRF_AB_GPIO15_IN_WIDTH 1
+#define FRF_AB_GPIO14_IN_LBN 46
+#define FRF_AB_GPIO14_IN_WIDTH 1
+#define FRF_AB_GPIO13_IN_LBN 45
+#define FRF_AB_GPIO13_IN_WIDTH 1
+#define FRF_AB_GPIO12_IN_LBN 44
+#define FRF_AB_GPIO12_IN_WIDTH 1
+#define FRF_AB_GPIO11_IN_LBN 43
+#define FRF_AB_GPIO11_IN_WIDTH 1
+#define FRF_AB_GPIO10_IN_LBN 42
+#define FRF_AB_GPIO10_IN_WIDTH 1
+#define FRF_AB_GPIO9_IN_LBN 41
+#define FRF_AB_GPIO9_IN_WIDTH 1
+#define FRF_AB_GPIO8_IN_LBN 40
+#define FRF_AB_GPIO8_IN_WIDTH 1
+#define FRF_AB_GPIO15_PWRUP_VALUE_LBN 39
+#define FRF_AB_GPIO15_PWRUP_VALUE_WIDTH 1
+#define FRF_AB_GPIO14_PWRUP_VALUE_LBN 38
+#define FRF_AB_GPIO14_PWRUP_VALUE_WIDTH 1
+#define FRF_AB_GPIO13_PWRUP_VALUE_LBN 37
+#define FRF_AB_GPIO13_PWRUP_VALUE_WIDTH 1
+#define FRF_AB_GPIO12_PWRUP_VALUE_LBN 36
+#define FRF_AB_GPIO12_PWRUP_VALUE_WIDTH 1
+#define FRF_AB_GPIO11_PWRUP_VALUE_LBN 35
+#define FRF_AB_GPIO11_PWRUP_VALUE_WIDTH 1
+#define FRF_AB_GPIO10_PWRUP_VALUE_LBN 34
+#define FRF_AB_GPIO10_PWRUP_VALUE_WIDTH 1
+#define FRF_AB_GPIO9_PWRUP_VALUE_LBN 33
+#define FRF_AB_GPIO9_PWRUP_VALUE_WIDTH 1
+#define FRF_AB_GPIO8_PWRUP_VALUE_LBN 32
+#define FRF_AB_GPIO8_PWRUP_VALUE_WIDTH 1
+#define FRF_AB_CLK156_OUT_EN_LBN 31
+#define FRF_AB_CLK156_OUT_EN_WIDTH 1
+#define FRF_AB_USE_NIC_CLK_LBN 30
+#define FRF_AB_USE_NIC_CLK_WIDTH 1
+#define FRF_AB_GPIO5_OEN_LBN 29
+#define FRF_AB_GPIO5_OEN_WIDTH 1
+#define FRF_AB_GPIO4_OEN_LBN 28
+#define FRF_AB_GPIO4_OEN_WIDTH 1
+#define FRF_AB_GPIO3_OEN_LBN 27
+#define FRF_AB_GPIO3_OEN_WIDTH 1
+#define FRF_AB_GPIO2_OEN_LBN 26
+#define FRF_AB_GPIO2_OEN_WIDTH 1
+#define FRF_AB_GPIO1_OEN_LBN 25
+#define FRF_AB_GPIO1_OEN_WIDTH 1
+#define FRF_AB_GPIO0_OEN_LBN 24
+#define FRF_AB_GPIO0_OEN_WIDTH 1
+#define FRF_AB_GPIO7_OUT_LBN 23
+#define FRF_AB_GPIO7_OUT_WIDTH 1
+#define FRF_AB_GPIO6_OUT_LBN 22
+#define FRF_AB_GPIO6_OUT_WIDTH 1
+#define FRF_AB_GPIO5_OUT_LBN 21
+#define FRF_AB_GPIO5_OUT_WIDTH 1
+#define FRF_AB_GPIO4_OUT_LBN 20
+#define FRF_AB_GPIO4_OUT_WIDTH 1
+#define FRF_AB_GPIO3_OUT_LBN 19
+#define FRF_AB_GPIO3_OUT_WIDTH 1
+#define FRF_AB_GPIO2_OUT_LBN 18
+#define FRF_AB_GPIO2_OUT_WIDTH 1
+#define FRF_AB_GPIO1_OUT_LBN 17
+#define FRF_AB_GPIO1_OUT_WIDTH 1
+#define FRF_AB_GPIO0_OUT_LBN 16
+#define FRF_AB_GPIO0_OUT_WIDTH 1
+#define FRF_AB_GPIO7_IN_LBN 15
+#define FRF_AB_GPIO7_IN_WIDTH 1
+#define FRF_AB_GPIO6_IN_LBN 14
+#define FRF_AB_GPIO6_IN_WIDTH 1
+#define FRF_AB_GPIO5_IN_LBN 13
+#define FRF_AB_GPIO5_IN_WIDTH 1
+#define FRF_AB_GPIO4_IN_LBN 12
+#define FRF_AB_GPIO4_IN_WIDTH 1
+#define FRF_AB_GPIO3_IN_LBN 11
+#define FRF_AB_GPIO3_IN_WIDTH 1
+#define FRF_AB_GPIO2_IN_LBN 10
+#define FRF_AB_GPIO2_IN_WIDTH 1
+#define FRF_AB_GPIO1_IN_LBN 9
+#define FRF_AB_GPIO1_IN_WIDTH 1
+#define FRF_AB_GPIO0_IN_LBN 8
+#define FRF_AB_GPIO0_IN_WIDTH 1
+#define FRF_AB_GPIO7_PWRUP_VALUE_LBN 7
+#define FRF_AB_GPIO7_PWRUP_VALUE_WIDTH 1
+#define FRF_AB_GPIO6_PWRUP_VALUE_LBN 6
+#define FRF_AB_GPIO6_PWRUP_VALUE_WIDTH 1
+#define FRF_AB_GPIO5_PWRUP_VALUE_LBN 5
+#define FRF_AB_GPIO5_PWRUP_VALUE_WIDTH 1
+#define FRF_AB_GPIO4_PWRUP_VALUE_LBN 4
+#define FRF_AB_GPIO4_PWRUP_VALUE_WIDTH 1
+#define FRF_AB_GPIO3_PWRUP_VALUE_LBN 3
+#define FRF_AB_GPIO3_PWRUP_VALUE_WIDTH 1
+#define FRF_AB_GPIO2_PWRUP_VALUE_LBN 2
+#define FRF_AB_GPIO2_PWRUP_VALUE_WIDTH 1
+#define FRF_AB_GPIO1_PWRUP_VALUE_LBN 1
+#define FRF_AB_GPIO1_PWRUP_VALUE_WIDTH 1
+#define FRF_AB_GPIO0_PWRUP_VALUE_LBN 0
+#define FRF_AB_GPIO0_PWRUP_VALUE_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_GLB_CTL_REG(128bit):
+ * Global control register
+ */
+#define FR_AB_GLB_CTL_REG_OFST 0x00000220
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_EXT_PHY_RST_CTL_LBN 63
+#define FRF_AB_EXT_PHY_RST_CTL_WIDTH 1
+#define FRF_AB_XAUI_SD_RST_CTL_LBN 62
+#define FRF_AB_XAUI_SD_RST_CTL_WIDTH 1
+#define FRF_AB_PCIE_SD_RST_CTL_LBN 61
+#define FRF_AB_PCIE_SD_RST_CTL_WIDTH 1
+#define FRF_AA_PCIX_RST_CTL_LBN 60
+#define FRF_AA_PCIX_RST_CTL_WIDTH 1
+#define FRF_BB_BIU_RST_CTL_LBN 60
+#define FRF_BB_BIU_RST_CTL_WIDTH 1
+#define FRF_AB_PCIE_STKY_RST_CTL_LBN 59
+#define FRF_AB_PCIE_STKY_RST_CTL_WIDTH 1
+#define FRF_AB_PCIE_NSTKY_RST_CTL_LBN 58
+#define FRF_AB_PCIE_NSTKY_RST_CTL_WIDTH 1
+#define FRF_AB_PCIE_CORE_RST_CTL_LBN 57
+#define FRF_AB_PCIE_CORE_RST_CTL_WIDTH 1
+#define FRF_AB_XGRX_RST_CTL_LBN 56
+#define FRF_AB_XGRX_RST_CTL_WIDTH 1
+#define FRF_AB_XGTX_RST_CTL_LBN 55
+#define FRF_AB_XGTX_RST_CTL_WIDTH 1
+#define FRF_AB_EM_RST_CTL_LBN 54
+#define FRF_AB_EM_RST_CTL_WIDTH 1
+#define FRF_AB_EV_RST_CTL_LBN 53
+#define FRF_AB_EV_RST_CTL_WIDTH 1
+#define FRF_AB_SR_RST_CTL_LBN 52
+#define FRF_AB_SR_RST_CTL_WIDTH 1
+#define FRF_AB_RX_RST_CTL_LBN 51
+#define FRF_AB_RX_RST_CTL_WIDTH 1
+#define FRF_AB_TX_RST_CTL_LBN 50
+#define FRF_AB_TX_RST_CTL_WIDTH 1
+#define FRF_AB_EE_RST_CTL_LBN 49
+#define FRF_AB_EE_RST_CTL_WIDTH 1
+#define FRF_AB_CS_RST_CTL_LBN 48
+#define FRF_AB_CS_RST_CTL_WIDTH 1
+#define FRF_AB_HOT_RST_CTL_LBN 40
+#define FRF_AB_HOT_RST_CTL_WIDTH 2
+#define FRF_AB_RST_EXT_PHY_LBN 31
+#define FRF_AB_RST_EXT_PHY_WIDTH 1
+#define FRF_AB_RST_XAUI_SD_LBN 30
+#define FRF_AB_RST_XAUI_SD_WIDTH 1
+#define FRF_AB_RST_PCIE_SD_LBN 29
+#define FRF_AB_RST_PCIE_SD_WIDTH 1
+#define FRF_AA_RST_PCIX_LBN 28
+#define FRF_AA_RST_PCIX_WIDTH 1
+#define FRF_BB_RST_BIU_LBN 28
+#define FRF_BB_RST_BIU_WIDTH 1
+#define FRF_AB_RST_PCIE_STKY_LBN 27
+#define FRF_AB_RST_PCIE_STKY_WIDTH 1
+#define FRF_AB_RST_PCIE_NSTKY_LBN 26
+#define FRF_AB_RST_PCIE_NSTKY_WIDTH 1
+#define FRF_AB_RST_PCIE_CORE_LBN 25
+#define FRF_AB_RST_PCIE_CORE_WIDTH 1
+#define FRF_AB_RST_XGRX_LBN 24
+#define FRF_AB_RST_XGRX_WIDTH 1
+#define FRF_AB_RST_XGTX_LBN 23
+#define FRF_AB_RST_XGTX_WIDTH 1
+#define FRF_AB_RST_EM_LBN 22
+#define FRF_AB_RST_EM_WIDTH 1
+#define FRF_AB_RST_EV_LBN 21
+#define FRF_AB_RST_EV_WIDTH 1
+#define FRF_AB_RST_SR_LBN 20
+#define FRF_AB_RST_SR_WIDTH 1
+#define FRF_AB_RST_RX_LBN 19
+#define FRF_AB_RST_RX_WIDTH 1
+#define FRF_AB_RST_TX_LBN 18
+#define FRF_AB_RST_TX_WIDTH 1
+#define FRF_AB_RST_SF_LBN 17
+#define FRF_AB_RST_SF_WIDTH 1
+#define FRF_AB_RST_CS_LBN 16
+#define FRF_AB_RST_CS_WIDTH 1
+#define FRF_AB_INT_RST_DUR_LBN 4
+#define FRF_AB_INT_RST_DUR_WIDTH 3
+#define FRF_AB_EXT_PHY_RST_DUR_LBN 1
+#define FRF_AB_EXT_PHY_RST_DUR_WIDTH 3
+#define FFE_AB_EXT_PHY_RST_DUR_10240US 7
+#define FFE_AB_EXT_PHY_RST_DUR_5120US 6
+#define FFE_AB_EXT_PHY_RST_DUR_2560US 5
+#define FFE_AB_EXT_PHY_RST_DUR_1280US 4
+#define FFE_AB_EXT_PHY_RST_DUR_640US 3
+#define FFE_AB_EXT_PHY_RST_DUR_320US 2
+#define FFE_AB_EXT_PHY_RST_DUR_160US 1
+#define FFE_AB_EXT_PHY_RST_DUR_80US 0
+#define FRF_AB_SWRST_LBN 0
+#define FRF_AB_SWRST_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_FATAL_INTR_REG_KER(128bit):
+ * Fatal interrupt register for Kernel
+ */
+#define FR_AZ_FATAL_INTR_REG_KER_OFST 0x00000230
+/* falcona0,falconb0,sienaa0=net_func_bar2 */
+
+#define FRF_CZ_SRAM_PERR_INT_P_KER_EN_LBN 44
+#define FRF_CZ_SRAM_PERR_INT_P_KER_EN_WIDTH 1
+#define FRF_AB_PCI_BUSERR_INT_KER_EN_LBN 43
+#define FRF_AB_PCI_BUSERR_INT_KER_EN_WIDTH 1
+#define FRF_CZ_MBU_PERR_INT_KER_EN_LBN 43
+#define FRF_CZ_MBU_PERR_INT_KER_EN_WIDTH 1
+#define FRF_AZ_SRAM_OOB_INT_KER_EN_LBN 42
+#define FRF_AZ_SRAM_OOB_INT_KER_EN_WIDTH 1
+#define FRF_AZ_BUFID_OOB_INT_KER_EN_LBN 41
+#define FRF_AZ_BUFID_OOB_INT_KER_EN_WIDTH 1
+#define FRF_AZ_MEM_PERR_INT_KER_EN_LBN 40
+#define FRF_AZ_MEM_PERR_INT_KER_EN_WIDTH 1
+#define FRF_AZ_RBUF_OWN_INT_KER_EN_LBN 39
+#define FRF_AZ_RBUF_OWN_INT_KER_EN_WIDTH 1
+#define FRF_AZ_TBUF_OWN_INT_KER_EN_LBN 38
+#define FRF_AZ_TBUF_OWN_INT_KER_EN_WIDTH 1
+#define FRF_AZ_RDESCQ_OWN_INT_KER_EN_LBN 37
+#define FRF_AZ_RDESCQ_OWN_INT_KER_EN_WIDTH 1
+#define FRF_AZ_TDESCQ_OWN_INT_KER_EN_LBN 36
+#define FRF_AZ_TDESCQ_OWN_INT_KER_EN_WIDTH 1
+#define FRF_AZ_EVQ_OWN_INT_KER_EN_LBN 35
+#define FRF_AZ_EVQ_OWN_INT_KER_EN_WIDTH 1
+#define FRF_AZ_EVF_OFLO_INT_KER_EN_LBN 34
+#define FRF_AZ_EVF_OFLO_INT_KER_EN_WIDTH 1
+#define FRF_AZ_ILL_ADR_INT_KER_EN_LBN 33
+#define FRF_AZ_ILL_ADR_INT_KER_EN_WIDTH 1
+#define FRF_AZ_SRM_PERR_INT_KER_EN_LBN 32
+#define FRF_AZ_SRM_PERR_INT_KER_EN_WIDTH 1
+#define FRF_CZ_SRAM_PERR_INT_P_KER_LBN 12
+#define FRF_CZ_SRAM_PERR_INT_P_KER_WIDTH 1
+#define FRF_AB_PCI_BUSERR_INT_KER_LBN 11
+#define FRF_AB_PCI_BUSERR_INT_KER_WIDTH 1
+#define FRF_CZ_MBU_PERR_INT_KER_LBN 11
+#define FRF_CZ_MBU_PERR_INT_KER_WIDTH 1
+#define FRF_AZ_SRAM_OOB_INT_KER_LBN 10
+#define FRF_AZ_SRAM_OOB_INT_KER_WIDTH 1
+#define FRF_AZ_BUFID_DC_OOB_INT_KER_LBN 9
+#define FRF_AZ_BUFID_DC_OOB_INT_KER_WIDTH 1
+#define FRF_AZ_MEM_PERR_INT_KER_LBN 8
+#define FRF_AZ_MEM_PERR_INT_KER_WIDTH 1
+#define FRF_AZ_RBUF_OWN_INT_KER_LBN 7
+#define FRF_AZ_RBUF_OWN_INT_KER_WIDTH 1
+#define FRF_AZ_TBUF_OWN_INT_KER_LBN 6
+#define FRF_AZ_TBUF_OWN_INT_KER_WIDTH 1
+#define FRF_AZ_RDESCQ_OWN_INT_KER_LBN 5
+#define FRF_AZ_RDESCQ_OWN_INT_KER_WIDTH 1
+#define FRF_AZ_TDESCQ_OWN_INT_KER_LBN 4
+#define FRF_AZ_TDESCQ_OWN_INT_KER_WIDTH 1
+#define FRF_AZ_EVQ_OWN_INT_KER_LBN 3
+#define FRF_AZ_EVQ_OWN_INT_KER_WIDTH 1
+#define FRF_AZ_EVF_OFLO_INT_KER_LBN 2
+#define FRF_AZ_EVF_OFLO_INT_KER_WIDTH 1
+#define FRF_AZ_ILL_ADR_INT_KER_LBN 1
+#define FRF_AZ_ILL_ADR_INT_KER_WIDTH 1
+#define FRF_AZ_SRM_PERR_INT_KER_LBN 0
+#define FRF_AZ_SRM_PERR_INT_KER_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_FATAL_INTR_REG_CHAR(128bit):
+ * Fatal interrupt register for Char
+ */
+#define FR_AZ_FATAL_INTR_REG_CHAR_OFST 0x00000240
+/* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_CZ_SRAM_PERR_INT_P_CHAR_EN_LBN 44
+#define FRF_CZ_SRAM_PERR_INT_P_CHAR_EN_WIDTH 1
+#define FRF_AB_PCI_BUSERR_INT_CHAR_EN_LBN 43
+#define FRF_AB_PCI_BUSERR_INT_CHAR_EN_WIDTH 1
+#define FRF_CZ_MBU_PERR_INT_CHAR_EN_LBN 43
+#define FRF_CZ_MBU_PERR_INT_CHAR_EN_WIDTH 1
+#define FRF_AZ_SRAM_OOB_INT_CHAR_EN_LBN 42
+#define FRF_AZ_SRAM_OOB_INT_CHAR_EN_WIDTH 1
+#define FRF_AZ_BUFID_OOB_INT_CHAR_EN_LBN 41
+#define FRF_AZ_BUFID_OOB_INT_CHAR_EN_WIDTH 1
+#define FRF_AZ_MEM_PERR_INT_CHAR_EN_LBN 40
+#define FRF_AZ_MEM_PERR_INT_CHAR_EN_WIDTH 1
+#define FRF_AZ_RBUF_OWN_INT_CHAR_EN_LBN 39
+#define FRF_AZ_RBUF_OWN_INT_CHAR_EN_WIDTH 1
+#define FRF_AZ_TBUF_OWN_INT_CHAR_EN_LBN 38
+#define FRF_AZ_TBUF_OWN_INT_CHAR_EN_WIDTH 1
+#define FRF_AZ_RDESCQ_OWN_INT_CHAR_EN_LBN 37
+#define FRF_AZ_RDESCQ_OWN_INT_CHAR_EN_WIDTH 1
+#define FRF_AZ_TDESCQ_OWN_INT_CHAR_EN_LBN 36
+#define FRF_AZ_TDESCQ_OWN_INT_CHAR_EN_WIDTH 1
+#define FRF_AZ_EVQ_OWN_INT_CHAR_EN_LBN 35
+#define FRF_AZ_EVQ_OWN_INT_CHAR_EN_WIDTH 1
+#define FRF_AZ_EVF_OFLO_INT_CHAR_EN_LBN 34
+#define FRF_AZ_EVF_OFLO_INT_CHAR_EN_WIDTH 1
+#define FRF_AZ_ILL_ADR_INT_CHAR_EN_LBN 33
+#define FRF_AZ_ILL_ADR_INT_CHAR_EN_WIDTH 1
+#define FRF_AZ_SRM_PERR_INT_CHAR_EN_LBN 32
+#define FRF_AZ_SRM_PERR_INT_CHAR_EN_WIDTH 1
+#define FRF_CZ_SRAM_PERR_INT_P_CHAR_LBN 12
+#define FRF_CZ_SRAM_PERR_INT_P_CHAR_WIDTH 1
+#define FRF_AB_PCI_BUSERR_INT_CHAR_LBN 11
+#define FRF_AB_PCI_BUSERR_INT_CHAR_WIDTH 1
+#define FRF_CZ_MBU_PERR_INT_CHAR_LBN 11
+#define FRF_CZ_MBU_PERR_INT_CHAR_WIDTH 1
+#define FRF_AZ_SRAM_OOB_INT_CHAR_LBN 10
+#define FRF_AZ_SRAM_OOB_INT_CHAR_WIDTH 1
+#define FRF_AZ_BUFID_DC_OOB_INT_CHAR_LBN 9
+#define FRF_AZ_BUFID_DC_OOB_INT_CHAR_WIDTH 1
+#define FRF_AZ_MEM_PERR_INT_CHAR_LBN 8
+#define FRF_AZ_MEM_PERR_INT_CHAR_WIDTH 1
+#define FRF_AZ_RBUF_OWN_INT_CHAR_LBN 7
+#define FRF_AZ_RBUF_OWN_INT_CHAR_WIDTH 1
+#define FRF_AZ_TBUF_OWN_INT_CHAR_LBN 6
+#define FRF_AZ_TBUF_OWN_INT_CHAR_WIDTH 1
+#define FRF_AZ_RDESCQ_OWN_INT_CHAR_LBN 5
+#define FRF_AZ_RDESCQ_OWN_INT_CHAR_WIDTH 1
+#define FRF_AZ_TDESCQ_OWN_INT_CHAR_LBN 4
+#define FRF_AZ_TDESCQ_OWN_INT_CHAR_WIDTH 1
+#define FRF_AZ_EVQ_OWN_INT_CHAR_LBN 3
+#define FRF_AZ_EVQ_OWN_INT_CHAR_WIDTH 1
+#define FRF_AZ_EVF_OFLO_INT_CHAR_LBN 2
+#define FRF_AZ_EVF_OFLO_INT_CHAR_WIDTH 1
+#define FRF_AZ_ILL_ADR_INT_CHAR_LBN 1
+#define FRF_AZ_ILL_ADR_INT_CHAR_WIDTH 1
+#define FRF_AZ_SRM_PERR_INT_CHAR_LBN 0
+#define FRF_AZ_SRM_PERR_INT_CHAR_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_DP_CTRL_REG(128bit):
+ * Datapath control register
+ */
+#define FR_AZ_DP_CTRL_REG_OFST 0x00000250
+/* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AZ_FLS_EVQ_ID_LBN 0
+#define FRF_AZ_FLS_EVQ_ID_WIDTH 12
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_MEM_STAT_REG(128bit):
+ * Memory status register
+ */
+#define FR_AZ_MEM_STAT_REG_OFST 0x00000260
+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_MEM_PERR_VEC_LBN 53
+#define FRF_AB_MEM_PERR_VEC_WIDTH 38
+#define FRF_AB_MBIST_CORR_LBN 38
+#define FRF_AB_MBIST_CORR_WIDTH 15
+#define FRF_AB_MBIST_ERR_LBN 0
+#define FRF_AB_MBIST_ERR_WIDTH 40
+#define FRF_CZ_MEM_PERR_VEC_LBN 0
+#define FRF_CZ_MEM_PERR_VEC_WIDTH 35
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_CS_DEBUG_REG(128bit):
+ * Debug register
+ */
+#define FR_AZ_CS_DEBUG_REG_OFST 0x00000270
+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_GLB_DEBUG2_SEL_LBN 50
+#define FRF_AB_GLB_DEBUG2_SEL_WIDTH 3
+#define FRF_AB_DEBUG_BLK_SEL2_LBN 47
+#define FRF_AB_DEBUG_BLK_SEL2_WIDTH 3
+#define FRF_AB_DEBUG_BLK_SEL1_LBN 44
+#define FRF_AB_DEBUG_BLK_SEL1_WIDTH 3
+#define FRF_AB_DEBUG_BLK_SEL0_LBN 41
+#define FRF_AB_DEBUG_BLK_SEL0_WIDTH 3
+#define FRF_CZ_CS_PORT_NUM_LBN 40
+#define FRF_CZ_CS_PORT_NUM_WIDTH 2
+#define FRF_AB_MISC_DEBUG_ADDR_LBN 36
+#define FRF_AB_MISC_DEBUG_ADDR_WIDTH 5
+#define FRF_AB_SERDES_DEBUG_ADDR_LBN 31
+#define FRF_AB_SERDES_DEBUG_ADDR_WIDTH 5
+#define FRF_CZ_CS_PORT_FPE_LBN 1
+#define FRF_CZ_CS_PORT_FPE_WIDTH 35
+#define FRF_AB_EM_DEBUG_ADDR_LBN 26
+#define FRF_AB_EM_DEBUG_ADDR_WIDTH 5
+#define FRF_AB_SR_DEBUG_ADDR_LBN 21
+#define FRF_AB_SR_DEBUG_ADDR_WIDTH 5
+#define FRF_AB_EV_DEBUG_ADDR_LBN 16
+#define FRF_AB_EV_DEBUG_ADDR_WIDTH 5
+#define FRF_AB_RX_DEBUG_ADDR_LBN 11
+#define FRF_AB_RX_DEBUG_ADDR_WIDTH 5
+#define FRF_AB_TX_DEBUG_ADDR_LBN 6
+#define FRF_AB_TX_DEBUG_ADDR_WIDTH 5
+#define FRF_AB_CS_BIU_DEBUG_ADDR_LBN 1
+#define FRF_AB_CS_BIU_DEBUG_ADDR_WIDTH 5
+#define FRF_AZ_CS_DEBUG_EN_LBN 0
+#define FRF_AZ_CS_DEBUG_EN_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_DRIVER_REG(128bit):
+ * Driver scratch register [0-7]
+ */
+#define FR_AZ_DRIVER_REG_OFST 0x00000280
+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
+#define FR_AZ_DRIVER_REG_STEP 16
+#define FR_AZ_DRIVER_REG_ROWS 8
+
+#define FRF_AZ_DRIVER_DW0_LBN 0
+#define FRF_AZ_DRIVER_DW0_WIDTH 32
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_ALTERA_BUILD_REG(128bit):
+ * Altera build register
+ */
+#define FR_AZ_ALTERA_BUILD_REG_OFST 0x00000300
+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AZ_ALTERA_BUILD_VER_LBN 0
+#define FRF_AZ_ALTERA_BUILD_VER_WIDTH 32
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_CSR_SPARE_REG(128bit):
+ * Spare register
+ */
+#define FR_AZ_CSR_SPARE_REG_OFST 0x00000310
+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_MEM_PERR_EN_LBN 64
+#define FRF_AB_MEM_PERR_EN_WIDTH 38
+#define FRF_CZ_MEM_PERR_EN_LBN 64
+#define FRF_CZ_MEM_PERR_EN_WIDTH 35
+#define FRF_AB_MEM_PERR_EN_TX_DATA_LBN 72
+#define FRF_AB_MEM_PERR_EN_TX_DATA_WIDTH 2
+#define FRF_AZ_CSR_SPARE_BITS_LBN 0
+#define FRF_AZ_CSR_SPARE_BITS_WIDTH 32
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_PCIE_SD_CTL0123_REG(128bit):
+ * PCIE SerDes control register 0 to 3
+ */
+#define FR_AB_PCIE_SD_CTL0123_REG_OFST 0x00000320
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_PCIE_TESTSIG_H_LBN 96
+#define FRF_AB_PCIE_TESTSIG_H_WIDTH 19
+#define FRF_AB_PCIE_TESTSIG_L_LBN 64
+#define FRF_AB_PCIE_TESTSIG_L_WIDTH 19
+#define FRF_AB_PCIE_OFFSET_LBN 56
+#define FRF_AB_PCIE_OFFSET_WIDTH 8
+#define FRF_AB_PCIE_OFFSETEN_H_LBN 55
+#define FRF_AB_PCIE_OFFSETEN_H_WIDTH 1
+#define FRF_AB_PCIE_OFFSETEN_L_LBN 54
+#define FRF_AB_PCIE_OFFSETEN_L_WIDTH 1
+#define FRF_AB_PCIE_HIVMODE_H_LBN 53
+#define FRF_AB_PCIE_HIVMODE_H_WIDTH 1
+#define FRF_AB_PCIE_HIVMODE_L_LBN 52
+#define FRF_AB_PCIE_HIVMODE_L_WIDTH 1
+#define FRF_AB_PCIE_PARRESET_H_LBN 51
+#define FRF_AB_PCIE_PARRESET_H_WIDTH 1
+#define FRF_AB_PCIE_PARRESET_L_LBN 50
+#define FRF_AB_PCIE_PARRESET_L_WIDTH 1
+#define FRF_AB_PCIE_LPBKWDRV_H_LBN 49
+#define FRF_AB_PCIE_LPBKWDRV_H_WIDTH 1
+#define FRF_AB_PCIE_LPBKWDRV_L_LBN 48
+#define FRF_AB_PCIE_LPBKWDRV_L_WIDTH 1
+#define FRF_AB_PCIE_LPBK_LBN 40
+#define FRF_AB_PCIE_LPBK_WIDTH 8
+#define FRF_AB_PCIE_PARLPBK_LBN 32
+#define FRF_AB_PCIE_PARLPBK_WIDTH 8
+#define FRF_AB_PCIE_RXTERMADJ_H_LBN 30
+#define FRF_AB_PCIE_RXTERMADJ_H_WIDTH 2
+#define FRF_AB_PCIE_RXTERMADJ_L_LBN 28
+#define FRF_AB_PCIE_RXTERMADJ_L_WIDTH 2
+#define FFE_AB_PCIE_RXTERMADJ_MIN15PCNT 3
+#define FFE_AB_PCIE_RXTERMADJ_PL10PCNT 2
+#define FFE_AB_PCIE_RXTERMADJ_MIN17PCNT 1
+#define FFE_AB_PCIE_RXTERMADJ_NOMNL 0
+#define FRF_AB_PCIE_TXTERMADJ_H_LBN 26
+#define FRF_AB_PCIE_TXTERMADJ_H_WIDTH 2
+#define FRF_AB_PCIE_TXTERMADJ_L_LBN 24
+#define FRF_AB_PCIE_TXTERMADJ_L_WIDTH 2
+#define FFE_AB_PCIE_TXTERMADJ_MIN15PCNT 3
+#define FFE_AB_PCIE_TXTERMADJ_PL10PCNT 2
+#define FFE_AB_PCIE_TXTERMADJ_MIN17PCNT 1
+#define FFE_AB_PCIE_TXTERMADJ_NOMNL 0
+#define FRF_AB_PCIE_RXEQCTL_H_LBN 18
+#define FRF_AB_PCIE_RXEQCTL_H_WIDTH 2
+#define FRF_AB_PCIE_RXEQCTL_L_LBN 16
+#define FRF_AB_PCIE_RXEQCTL_L_WIDTH 2
+#define FFE_AB_PCIE_RXEQCTL_OFF_ALT 3
+#define FFE_AB_PCIE_RXEQCTL_OFF 2
+#define FFE_AB_PCIE_RXEQCTL_MIN 1
+#define FFE_AB_PCIE_RXEQCTL_MAX 0
+#define FRF_AB_PCIE_HIDRV_LBN 8
+#define FRF_AB_PCIE_HIDRV_WIDTH 8
+#define FRF_AB_PCIE_LODRV_LBN 0
+#define FRF_AB_PCIE_LODRV_WIDTH 8
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_PCIE_SD_CTL45_REG(128bit):
+ * PCIE SerDes control register 4 and 5
+ */
+#define FR_AB_PCIE_SD_CTL45_REG_OFST 0x00000330
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_PCIE_DTX7_LBN 60
+#define FRF_AB_PCIE_DTX7_WIDTH 4
+#define FRF_AB_PCIE_DTX6_LBN 56
+#define FRF_AB_PCIE_DTX6_WIDTH 4
+#define FRF_AB_PCIE_DTX5_LBN 52
+#define FRF_AB_PCIE_DTX5_WIDTH 4
+#define FRF_AB_PCIE_DTX4_LBN 48
+#define FRF_AB_PCIE_DTX4_WIDTH 4
+#define FRF_AB_PCIE_DTX3_LBN 44
+#define FRF_AB_PCIE_DTX3_WIDTH 4
+#define FRF_AB_PCIE_DTX2_LBN 40
+#define FRF_AB_PCIE_DTX2_WIDTH 4
+#define FRF_AB_PCIE_DTX1_LBN 36
+#define FRF_AB_PCIE_DTX1_WIDTH 4
+#define FRF_AB_PCIE_DTX0_LBN 32
+#define FRF_AB_PCIE_DTX0_WIDTH 4
+#define FRF_AB_PCIE_DEQ7_LBN 28
+#define FRF_AB_PCIE_DEQ7_WIDTH 4
+#define FRF_AB_PCIE_DEQ6_LBN 24
+#define FRF_AB_PCIE_DEQ6_WIDTH 4
+#define FRF_AB_PCIE_DEQ5_LBN 20
+#define FRF_AB_PCIE_DEQ5_WIDTH 4
+#define FRF_AB_PCIE_DEQ4_LBN 16
+#define FRF_AB_PCIE_DEQ4_WIDTH 4
+#define FRF_AB_PCIE_DEQ3_LBN 12
+#define FRF_AB_PCIE_DEQ3_WIDTH 4
+#define FRF_AB_PCIE_DEQ2_LBN 8
+#define FRF_AB_PCIE_DEQ2_WIDTH 4
+#define FRF_AB_PCIE_DEQ1_LBN 4
+#define FRF_AB_PCIE_DEQ1_WIDTH 4
+#define FRF_AB_PCIE_DEQ0_LBN 0
+#define FRF_AB_PCIE_DEQ0_WIDTH 4
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_PCIE_PCS_CTL_STAT_REG(128bit):
+ * PCIE PCS control and status register
+ */
+#define FR_AB_PCIE_PCS_CTL_STAT_REG_OFST 0x00000340
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_PCIE_PRBSERRCOUNT0_H_LBN 52
+#define FRF_AB_PCIE_PRBSERRCOUNT0_H_WIDTH 4
+#define FRF_AB_PCIE_PRBSERRCOUNT0_L_LBN 48
+#define FRF_AB_PCIE_PRBSERRCOUNT0_L_WIDTH 4
+#define FRF_AB_PCIE_PRBSERR_LBN 40
+#define FRF_AB_PCIE_PRBSERR_WIDTH 8
+#define FRF_AB_PCIE_PRBSERRH0_LBN 32
+#define FRF_AB_PCIE_PRBSERRH0_WIDTH 8
+#define FRF_AB_PCIE_FASTINIT_H_LBN 15
+#define FRF_AB_PCIE_FASTINIT_H_WIDTH 1
+#define FRF_AB_PCIE_FASTINIT_L_LBN 14
+#define FRF_AB_PCIE_FASTINIT_L_WIDTH 1
+#define FRF_AB_PCIE_CTCDISABLE_H_LBN 13
+#define FRF_AB_PCIE_CTCDISABLE_H_WIDTH 1
+#define FRF_AB_PCIE_CTCDISABLE_L_LBN 12
+#define FRF_AB_PCIE_CTCDISABLE_L_WIDTH 1
+#define FRF_AB_PCIE_PRBSSYNC_H_LBN 11
+#define FRF_AB_PCIE_PRBSSYNC_H_WIDTH 1
+#define FRF_AB_PCIE_PRBSSYNC_L_LBN 10
+#define FRF_AB_PCIE_PRBSSYNC_L_WIDTH 1
+#define FRF_AB_PCIE_PRBSERRACK_H_LBN 9
+#define FRF_AB_PCIE_PRBSERRACK_H_WIDTH 1
+#define FRF_AB_PCIE_PRBSERRACK_L_LBN 8
+#define FRF_AB_PCIE_PRBSERRACK_L_WIDTH 1
+#define FRF_AB_PCIE_PRBSSEL_LBN 0
+#define FRF_AB_PCIE_PRBSSEL_WIDTH 8
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_BB_DEBUG_DATA_OUT_REG(128bit):
+ * Live Debug and Debug 2 out ports
+ */
+#define FR_BB_DEBUG_DATA_OUT_REG_OFST 0x00000350
+/* falconb0=net_func_bar2 */
+
+#define FRF_BB_DEBUG2_PORT_LBN 25
+#define FRF_BB_DEBUG2_PORT_WIDTH 15
+#define FRF_BB_DEBUG1_PORT_LBN 0
+#define FRF_BB_DEBUG1_PORT_WIDTH 25
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_BZ_EVQ_RPTR_REGP0(32bit):
+ * Event queue read pointer register
+ */
+#define FR_BZ_EVQ_RPTR_REGP0_OFST 0x00000400
+/* falconb0,sienaa0=net_func_bar2 */
+#define FR_BZ_EVQ_RPTR_REGP0_STEP 8192
+#define FR_BZ_EVQ_RPTR_REGP0_ROWS 1024
+/*
+ * FR_AA_EVQ_RPTR_REG_KER(32bit):
+ * Event queue read pointer register
+ */
+#define FR_AA_EVQ_RPTR_REG_KER_OFST 0x00011b00
+/* falcona0=net_func_bar2 */
+#define FR_AA_EVQ_RPTR_REG_KER_STEP 4
+#define FR_AA_EVQ_RPTR_REG_KER_ROWS 4
+/*
+ * FR_AZ_EVQ_RPTR_REG(32bit):
+ * Event queue read pointer register
+ */
+#define FR_AZ_EVQ_RPTR_REG_OFST 0x00fa0000
+/* falconb0=net_func_bar2,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
+#define FR_AZ_EVQ_RPTR_REG_STEP 16
+#define FR_AB_EVQ_RPTR_REG_ROWS 4096
+#define FR_CZ_EVQ_RPTR_REG_ROWS 1024
+/*
+ * FR_BB_EVQ_RPTR_REGP123(32bit):
+ * Event queue read pointer register
+ */
+#define FR_BB_EVQ_RPTR_REGP123_OFST 0x01000400
+/* falconb0=net_func_bar2 */
+#define FR_BB_EVQ_RPTR_REGP123_STEP 8192
+#define FR_BB_EVQ_RPTR_REGP123_ROWS 3072
+
+#define FRF_AZ_EVQ_RPTR_VLD_LBN 15
+#define FRF_AZ_EVQ_RPTR_VLD_WIDTH 1
+#define FRF_AZ_EVQ_RPTR_LBN 0
+#define FRF_AZ_EVQ_RPTR_WIDTH 15
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_BZ_TIMER_COMMAND_REGP0(128bit):
+ * Timer Command Registers
+ */
+#define FR_BZ_TIMER_COMMAND_REGP0_OFST 0x00000420
+/* falconb0,sienaa0=net_func_bar2 */
+#define FR_AZ_TIMER_COMMAND_REGP0_STEP 8192
+#define FR_BZ_TIMER_COMMAND_REGP0_ROWS 1024
+/*
+ * FR_AA_TIMER_COMMAND_REG_KER(128bit):
+ * Timer Command Registers
+ */
+#define FR_AA_TIMER_COMMAND_REG_KER_OFST 0x00000420
+/* falcona0=net_func_bar2 */
+#define FR_AA_TIMER_COMMAND_REG_KER_STEP 8192
+#define FR_AA_TIMER_COMMAND_REG_KER_ROWS 4
+/*
+ * FR_AB_TIMER_COMMAND_REGP123(128bit):
+ * Timer Command Registers
+ */
+#define FR_AB_TIMER_COMMAND_REGP123_OFST 0x01000420
+/* falconb0=net_func_bar2,falcona0=char_func_bar0 */
+#define FR_AB_TIMER_COMMAND_REGP123_STEP 8192
+#define FR_AB_TIMER_COMMAND_REGP123_ROWS 3072
+/*
+ * FR_AA_TIMER_COMMAND_REGP0(128bit):
+ * Timer Command Registers
+ */
+#define FR_AA_TIMER_COMMAND_REGP0_OFST 0x00008420
+/* falcona0=char_func_bar0 */
+/* FR_AZ_TIMER_COMMAND_REGP0_STEP 8192 */
+#define FR_AA_TIMER_COMMAND_REGP0_ROWS 1020
+
+#define FRF_CZ_TC_TIMER_MODE_LBN 14
+#define FRF_CZ_TC_TIMER_MODE_WIDTH 2
+#define FRF_AB_TC_TIMER_MODE_LBN 12
+#define FRF_AB_TC_TIMER_MODE_WIDTH 2
+#define FRF_CZ_TC_TIMER_VAL_LBN 0
+#define FRF_CZ_TC_TIMER_VAL_WIDTH 14
+#define FRF_AB_TC_TIMER_VAL_LBN 0
+#define FRF_AB_TC_TIMER_VAL_WIDTH 12
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_DRV_EV_REG(128bit):
+ * Driver generated event register
+ */
+#define FR_AZ_DRV_EV_REG_OFST 0x00000440
+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AZ_DRV_EV_QID_LBN 64
+#define FRF_AZ_DRV_EV_QID_WIDTH 12
+#define FRF_AZ_DRV_EV_DATA_LBN 0
+#define FRF_AZ_DRV_EV_DATA_WIDTH 64
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_EVQ_CTL_REG(128bit):
+ * Event queue control register
+ */
+#define FR_AZ_EVQ_CTL_REG_OFST 0x00000450
+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_CZ_RX_EVQ_WAKEUP_MASK_LBN 15
+#define FRF_CZ_RX_EVQ_WAKEUP_MASK_WIDTH 10
+#define FRF_BB_RX_EVQ_WAKEUP_MASK_LBN 15
+#define FRF_BB_RX_EVQ_WAKEUP_MASK_WIDTH 6
+#define FRF_AZ_EVQ_OWNERR_CTL_LBN 14
+#define FRF_AZ_EVQ_OWNERR_CTL_WIDTH 1
+#define FRF_AZ_EVQ_FIFO_AF_TH_LBN 7
+#define FRF_AZ_EVQ_FIFO_AF_TH_WIDTH 7
+#define FRF_AZ_EVQ_FIFO_NOTAF_TH_LBN 0
+#define FRF_AZ_EVQ_FIFO_NOTAF_TH_WIDTH 7
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_EVQ_CNT1_REG(128bit):
+ * Event counter 1 register
+ */
+#define FR_AZ_EVQ_CNT1_REG_OFST 0x00000460
+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AZ_EVQ_CNT_PRE_FIFO_LBN 120
+#define FRF_AZ_EVQ_CNT_PRE_FIFO_WIDTH 7
+#define FRF_AZ_EVQ_CNT_TOBIU_LBN 100
+#define FRF_AZ_EVQ_CNT_TOBIU_WIDTH 20
+#define FRF_AZ_EVQ_TX_REQ_CNT_LBN 80
+#define FRF_AZ_EVQ_TX_REQ_CNT_WIDTH 20
+#define FRF_AZ_EVQ_RX_REQ_CNT_LBN 60
+#define FRF_AZ_EVQ_RX_REQ_CNT_WIDTH 20
+#define FRF_AZ_EVQ_EM_REQ_CNT_LBN 40
+#define FRF_AZ_EVQ_EM_REQ_CNT_WIDTH 20
+#define FRF_AZ_EVQ_CSR_REQ_CNT_LBN 20
+#define FRF_AZ_EVQ_CSR_REQ_CNT_WIDTH 20
+#define FRF_AZ_EVQ_ERR_REQ_CNT_LBN 0
+#define FRF_AZ_EVQ_ERR_REQ_CNT_WIDTH 20
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_EVQ_CNT2_REG(128bit):
+ * Event counter 2 register
+ */
+#define FR_AZ_EVQ_CNT2_REG_OFST 0x00000470
+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AZ_EVQ_UPD_REQ_CNT_LBN 104
+#define FRF_AZ_EVQ_UPD_REQ_CNT_WIDTH 20
+#define FRF_AZ_EVQ_CLR_REQ_CNT_LBN 84
+#define FRF_AZ_EVQ_CLR_REQ_CNT_WIDTH 20
+#define FRF_AZ_EVQ_RDY_CNT_LBN 80
+#define FRF_AZ_EVQ_RDY_CNT_WIDTH 4
+#define FRF_AZ_EVQ_WU_REQ_CNT_LBN 60
+#define FRF_AZ_EVQ_WU_REQ_CNT_WIDTH 20
+#define FRF_AZ_EVQ_WET_REQ_CNT_LBN 40
+#define FRF_AZ_EVQ_WET_REQ_CNT_WIDTH 20
+#define FRF_AZ_EVQ_INIT_REQ_CNT_LBN 20
+#define FRF_AZ_EVQ_INIT_REQ_CNT_WIDTH 20
+#define FRF_AZ_EVQ_TM_REQ_CNT_LBN 0
+#define FRF_AZ_EVQ_TM_REQ_CNT_WIDTH 20
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_CZ_USR_EV_REG(32bit):
+ * Event mailbox register
+ */
+#define FR_CZ_USR_EV_REG_OFST 0x00000540
+/* sienaa0=net_func_bar2 */
+#define FR_CZ_USR_EV_REG_STEP 8192
+#define FR_CZ_USR_EV_REG_ROWS 1024
+
+#define FRF_CZ_USR_EV_DATA_LBN 0
+#define FRF_CZ_USR_EV_DATA_WIDTH 32
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_BUF_TBL_CFG_REG(128bit):
+ * Buffer table configuration register
+ */
+#define FR_AZ_BUF_TBL_CFG_REG_OFST 0x00000600
+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AZ_BUF_TBL_MODE_LBN 3
+#define FRF_AZ_BUF_TBL_MODE_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_SRM_RX_DC_CFG_REG(128bit):
+ * SRAM receive descriptor cache configuration register
+ */
+#define FR_AZ_SRM_RX_DC_CFG_REG_OFST 0x00000610
+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AZ_SRM_CLK_TMP_EN_LBN 21
+#define FRF_AZ_SRM_CLK_TMP_EN_WIDTH 1
+#define FRF_AZ_SRM_RX_DC_BASE_ADR_LBN 0
+#define FRF_AZ_SRM_RX_DC_BASE_ADR_WIDTH 21
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_SRM_TX_DC_CFG_REG(128bit):
+ * SRAM transmit descriptor cache configuration register
+ */
+#define FR_AZ_SRM_TX_DC_CFG_REG_OFST 0x00000620
+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AZ_SRM_TX_DC_BASE_ADR_LBN 0
+#define FRF_AZ_SRM_TX_DC_BASE_ADR_WIDTH 21
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_SRM_CFG_REG(128bit):
+ * SRAM configuration register
+ */
+#define FR_AZ_SRM_CFG_REG_OFST 0x00000630
+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AZ_SRM_OOB_ADR_INTEN_LBN 5
+#define FRF_AZ_SRM_OOB_ADR_INTEN_WIDTH 1
+#define FRF_AZ_SRM_OOB_BUF_INTEN_LBN 4
+#define FRF_AZ_SRM_OOB_BUF_INTEN_WIDTH 1
+#define FRF_AZ_SRM_INIT_EN_LBN 3
+#define FRF_AZ_SRM_INIT_EN_WIDTH 1
+#define FRF_AZ_SRM_NUM_BANK_LBN 2
+#define FRF_AZ_SRM_NUM_BANK_WIDTH 1
+#define FRF_AZ_SRM_BANK_SIZE_LBN 0
+#define FRF_AZ_SRM_BANK_SIZE_WIDTH 2
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_BUF_TBL_UPD_REG(128bit):
+ * Buffer table update register
+ */
+#define FR_AZ_BUF_TBL_UPD_REG_OFST 0x00000650
+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AZ_BUF_UPD_CMD_LBN 63
+#define FRF_AZ_BUF_UPD_CMD_WIDTH 1
+#define FRF_AZ_BUF_CLR_CMD_LBN 62
+#define FRF_AZ_BUF_CLR_CMD_WIDTH 1
+#define FRF_AZ_BUF_CLR_END_ID_LBN 32
+#define FRF_AZ_BUF_CLR_END_ID_WIDTH 20
+#define FRF_AZ_BUF_CLR_START_ID_LBN 0
+#define FRF_AZ_BUF_CLR_START_ID_WIDTH 20
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_SRM_UPD_EVQ_REG(128bit):
+ * Buffer table update register
+ */
+#define FR_AZ_SRM_UPD_EVQ_REG_OFST 0x00000660
+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AZ_SRM_UPD_EVQ_ID_LBN 0
+#define FRF_AZ_SRM_UPD_EVQ_ID_WIDTH 12
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_SRAM_PARITY_REG(128bit):
+ * SRAM parity register.
+ */
+#define FR_AZ_SRAM_PARITY_REG_OFST 0x00000670
+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_CZ_BYPASS_ECC_LBN 3
+#define FRF_CZ_BYPASS_ECC_WIDTH 1
+#define FRF_CZ_SEC_INT_LBN 2
+#define FRF_CZ_SEC_INT_WIDTH 1
+#define FRF_CZ_FORCE_SRAM_DOUBLE_ERR_LBN 1
+#define FRF_CZ_FORCE_SRAM_DOUBLE_ERR_WIDTH 1
+#define FRF_AB_FORCE_SRAM_PERR_LBN 0
+#define FRF_AB_FORCE_SRAM_PERR_WIDTH 1
+#define FRF_CZ_FORCE_SRAM_SINGLE_ERR_LBN 0
+#define FRF_CZ_FORCE_SRAM_SINGLE_ERR_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_RX_CFG_REG(128bit):
+ * Receive configuration register
+ */
+#define FR_AZ_RX_CFG_REG_OFST 0x00000800
+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_CZ_RX_MIN_KBUF_SIZE_LBN 72
+#define FRF_CZ_RX_MIN_KBUF_SIZE_WIDTH 14
+#define FRF_CZ_RX_HDR_SPLIT_EN_LBN 71
+#define FRF_CZ_RX_HDR_SPLIT_EN_WIDTH 1
+#define FRF_CZ_RX_HDR_SPLIT_PLD_BUF_SIZE_LBN 62
+#define FRF_CZ_RX_HDR_SPLIT_PLD_BUF_SIZE_WIDTH 9
+#define FRF_CZ_RX_HDR_SPLIT_HDR_BUF_SIZE_LBN 53
+#define FRF_CZ_RX_HDR_SPLIT_HDR_BUF_SIZE_WIDTH 9
+#define FRF_CZ_RX_PRE_RFF_IPG_LBN 49
+#define FRF_CZ_RX_PRE_RFF_IPG_WIDTH 4
+#define FRF_BZ_RX_TCP_SUP_LBN 48
+#define FRF_BZ_RX_TCP_SUP_WIDTH 1
+#define FRF_BZ_RX_INGR_EN_LBN 47
+#define FRF_BZ_RX_INGR_EN_WIDTH 1
+#define FRF_BZ_RX_IP_HASH_LBN 46
+#define FRF_BZ_RX_IP_HASH_WIDTH 1
+#define FRF_BZ_RX_HASH_ALG_LBN 45
+#define FRF_BZ_RX_HASH_ALG_WIDTH 1
+#define FRF_BZ_RX_HASH_INSRT_HDR_LBN 44
+#define FRF_BZ_RX_HASH_INSRT_HDR_WIDTH 1
+#define FRF_BZ_RX_DESC_PUSH_EN_LBN 43
+#define FRF_BZ_RX_DESC_PUSH_EN_WIDTH 1
+#define FRF_BZ_RX_RDW_PATCH_EN_LBN 42
+#define FRF_BZ_RX_RDW_PATCH_EN_WIDTH 1
+#define FRF_BB_RX_PCI_BURST_SIZE_LBN 39
+#define FRF_BB_RX_PCI_BURST_SIZE_WIDTH 3
+#define FRF_BZ_RX_OWNERR_CTL_LBN 38
+#define FRF_BZ_RX_OWNERR_CTL_WIDTH 1
+#define FRF_BZ_RX_XON_TX_TH_LBN 33
+#define FRF_BZ_RX_XON_TX_TH_WIDTH 5
+#define FRF_AA_RX_DESC_PUSH_EN_LBN 35
+#define FRF_AA_RX_DESC_PUSH_EN_WIDTH 1
+#define FRF_AA_RX_RDW_PATCH_EN_LBN 34
+#define FRF_AA_RX_RDW_PATCH_EN_WIDTH 1
+#define FRF_AA_RX_PCI_BURST_SIZE_LBN 31
+#define FRF_AA_RX_PCI_BURST_SIZE_WIDTH 3
+#define FRF_BZ_RX_XOFF_TX_TH_LBN 28
+#define FRF_BZ_RX_XOFF_TX_TH_WIDTH 5
+#define FRF_AA_RX_OWNERR_CTL_LBN 30
+#define FRF_AA_RX_OWNERR_CTL_WIDTH 1
+#define FRF_AA_RX_XON_TX_TH_LBN 25
+#define FRF_AA_RX_XON_TX_TH_WIDTH 5
+#define FRF_BZ_RX_USR_BUF_SIZE_LBN 19
+#define FRF_BZ_RX_USR_BUF_SIZE_WIDTH 9
+#define FRF_AA_RX_XOFF_TX_TH_LBN 20
+#define FRF_AA_RX_XOFF_TX_TH_WIDTH 5
+#define FRF_AA_RX_USR_BUF_SIZE_LBN 11
+#define FRF_AA_RX_USR_BUF_SIZE_WIDTH 9
+#define FRF_BZ_RX_XON_MAC_TH_LBN 10
+#define FRF_BZ_RX_XON_MAC_TH_WIDTH 9
+#define FRF_AA_RX_XON_MAC_TH_LBN 6
+#define FRF_AA_RX_XON_MAC_TH_WIDTH 5
+#define FRF_BZ_RX_XOFF_MAC_TH_LBN 1
+#define FRF_BZ_RX_XOFF_MAC_TH_WIDTH 9
+#define FRF_AA_RX_XOFF_MAC_TH_LBN 1
+#define FRF_AA_RX_XOFF_MAC_TH_WIDTH 5
+#define FRF_AZ_RX_XOFF_MAC_EN_LBN 0
+#define FRF_AZ_RX_XOFF_MAC_EN_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_RX_FILTER_CTL_REG(128bit):
+ * Receive filter control registers
+ */
+#define FR_AZ_RX_FILTER_CTL_REG_OFST 0x00000810
+/* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_CZ_ETHERNET_WILDCARD_SEARCH_LIMIT_LBN 94
+#define FRF_CZ_ETHERNET_WILDCARD_SEARCH_LIMIT_WIDTH 8
+#define FRF_CZ_ETHERNET_FULL_SEARCH_LIMIT_LBN 86
+#define FRF_CZ_ETHERNET_FULL_SEARCH_LIMIT_WIDTH 8
+#define FRF_CZ_RX_FILTER_ALL_VLAN_ETHERTYPES_LBN 85
+#define FRF_CZ_RX_FILTER_ALL_VLAN_ETHERTYPES_WIDTH 1
+#define FRF_CZ_RX_VLAN_MATCH_ETHERTYPE_LBN 69
+#define FRF_CZ_RX_VLAN_MATCH_ETHERTYPE_WIDTH 16
+#define FRF_CZ_MULTICAST_NOMATCH_Q_ID_LBN 57
+#define FRF_CZ_MULTICAST_NOMATCH_Q_ID_WIDTH 12
+#define FRF_CZ_MULTICAST_NOMATCH_RSS_ENABLED_LBN 56
+#define FRF_CZ_MULTICAST_NOMATCH_RSS_ENABLED_WIDTH 1
+#define FRF_CZ_MULTICAST_NOMATCH_IP_OVERRIDE_LBN 55
+#define FRF_CZ_MULTICAST_NOMATCH_IP_OVERRIDE_WIDTH 1
+#define FRF_CZ_UNICAST_NOMATCH_Q_ID_LBN 43
+#define FRF_CZ_UNICAST_NOMATCH_Q_ID_WIDTH 12
+#define FRF_CZ_UNICAST_NOMATCH_RSS_ENABLED_LBN 42
+#define FRF_CZ_UNICAST_NOMATCH_RSS_ENABLED_WIDTH 1
+#define FRF_CZ_UNICAST_NOMATCH_IP_OVERRIDE_LBN 41
+#define FRF_CZ_UNICAST_NOMATCH_IP_OVERRIDE_WIDTH 1
+#define FRF_BZ_SCATTER_ENBL_NO_MATCH_Q_LBN 40
+#define FRF_BZ_SCATTER_ENBL_NO_MATCH_Q_WIDTH 1
+#define FRF_AZ_UDP_FULL_SRCH_LIMIT_LBN 32
+#define FRF_AZ_UDP_FULL_SRCH_LIMIT_WIDTH 8
+#define FRF_AZ_NUM_KER_LBN 24
+#define FRF_AZ_NUM_KER_WIDTH 2
+#define FRF_AZ_UDP_WILD_SRCH_LIMIT_LBN 16
+#define FRF_AZ_UDP_WILD_SRCH_LIMIT_WIDTH 8
+#define FRF_AZ_TCP_WILD_SRCH_LIMIT_LBN 8
+#define FRF_AZ_TCP_WILD_SRCH_LIMIT_WIDTH 8
+#define FRF_AZ_TCP_FULL_SRCH_LIMIT_LBN 0
+#define FRF_AZ_TCP_FULL_SRCH_LIMIT_WIDTH 8
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_RX_FLUSH_DESCQ_REG(128bit):
+ * Receive flush descriptor queue register
+ */
+#define FR_AZ_RX_FLUSH_DESCQ_REG_OFST 0x00000820
+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AZ_RX_FLUSH_DESCQ_CMD_LBN 24
+#define FRF_AZ_RX_FLUSH_DESCQ_CMD_WIDTH 1
+#define FRF_AZ_RX_FLUSH_DESCQ_LBN 0
+#define FRF_AZ_RX_FLUSH_DESCQ_WIDTH 12
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_BZ_RX_DESC_UPD_REGP0(128bit):
+ * Receive descriptor update register.
+ */
+#define FR_BZ_RX_DESC_UPD_REGP0_OFST 0x00000830
+/* falconb0,sienaa0=net_func_bar2 */
+#define FR_AZ_RX_DESC_UPD_REGP0_STEP 8192
+#define FR_BZ_RX_DESC_UPD_REGP0_ROWS 1024
+/*
+ * FR_AA_RX_DESC_UPD_REG_KER(128bit):
+ * Receive descriptor update register.
+ */
+#define FR_AA_RX_DESC_UPD_REG_KER_OFST 0x00000830
+/* falcona0=net_func_bar2 */
+#define FR_AA_RX_DESC_UPD_REG_KER_STEP 8192
+#define FR_AA_RX_DESC_UPD_REG_KER_ROWS 4
+/*
+ * FR_AB_RX_DESC_UPD_REGP123(128bit):
+ * Receive descriptor update register.
+ */
+#define FR_AB_RX_DESC_UPD_REGP123_OFST 0x01000830
+/* falconb0=net_func_bar2,falcona0=char_func_bar0 */
+#define FR_AB_RX_DESC_UPD_REGP123_STEP 8192
+#define FR_AB_RX_DESC_UPD_REGP123_ROWS 3072
+/*
+ * FR_AA_RX_DESC_UPD_REGP0(128bit):
+ * Receive descriptor update register.
+ */
+#define FR_AA_RX_DESC_UPD_REGP0_OFST 0x00008830
+/* falcona0=char_func_bar0 */
+/* FR_AZ_RX_DESC_UPD_REGP0_STEP 8192 */
+#define FR_AA_RX_DESC_UPD_REGP0_ROWS 1020
+
+#define FRF_AZ_RX_DESC_WPTR_LBN 96
+#define FRF_AZ_RX_DESC_WPTR_WIDTH 12
+#define FRF_AZ_RX_DESC_PUSH_CMD_LBN 95
+#define FRF_AZ_RX_DESC_PUSH_CMD_WIDTH 1
+#define FRF_AZ_RX_DESC_LBN 0
+#define FRF_AZ_RX_DESC_WIDTH 64
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_RX_DC_CFG_REG(128bit):
+ * Receive descriptor cache configuration register
+ */
+#define FR_AZ_RX_DC_CFG_REG_OFST 0x00000840
+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_RX_MAX_PF_LBN 2
+#define FRF_AB_RX_MAX_PF_WIDTH 2
+#define FRF_AZ_RX_DC_SIZE_LBN 0
+#define FRF_AZ_RX_DC_SIZE_WIDTH 2
+#define FFE_AZ_RX_DC_SIZE_64 3
+#define FFE_AZ_RX_DC_SIZE_32 2
+#define FFE_AZ_RX_DC_SIZE_16 1
+#define FFE_AZ_RX_DC_SIZE_8 0
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_RX_DC_PF_WM_REG(128bit):
+ * Receive descriptor cache pre-fetch watermark register
+ */
+#define FR_AZ_RX_DC_PF_WM_REG_OFST 0x00000850
+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AZ_RX_DC_PF_HWM_LBN 6
+#define FRF_AZ_RX_DC_PF_HWM_WIDTH 6
+#define FRF_AZ_RX_DC_PF_LWM_LBN 0
+#define FRF_AZ_RX_DC_PF_LWM_WIDTH 6
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_BZ_RX_RSS_TKEY_REG(128bit):
+ * RSS Toeplitz hash key
+ */
+#define FR_BZ_RX_RSS_TKEY_REG_OFST 0x00000860
+/* falconb0,sienaa0=net_func_bar2 */
+
+#define FRF_BZ_RX_RSS_TKEY_HI_LBN 64
+#define FRF_BZ_RX_RSS_TKEY_HI_WIDTH 64
+#define FRF_BZ_RX_RSS_TKEY_LO_LBN 0
+#define FRF_BZ_RX_RSS_TKEY_LO_WIDTH 64
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_RX_NODESC_DROP_REG(128bit):
+ * Receive dropped packet counter register
+ */
+#define FR_AZ_RX_NODESC_DROP_REG_OFST 0x00000880
+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_CZ_RX_NODESC_DROP_CNT_LBN 0
+#define FRF_CZ_RX_NODESC_DROP_CNT_WIDTH 32
+#define FRF_AB_RX_NODESC_DROP_CNT_LBN 0
+#define FRF_AB_RX_NODESC_DROP_CNT_WIDTH 16
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AA_RX_SELF_RST_REG(128bit):
+ * Receive self reset register
+ */
+#define FR_AA_RX_SELF_RST_REG_OFST 0x00000890
+/* falcona0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AA_RX_ISCSI_DIS_LBN 17
+#define FRF_AA_RX_ISCSI_DIS_WIDTH 1
+#define FRF_AA_RX_SW_RST_REG_LBN 16
+#define FRF_AA_RX_SW_RST_REG_WIDTH 1
+#define FRF_AA_RX_SELF_RST_EN_LBN 8
+#define FRF_AA_RX_SELF_RST_EN_WIDTH 1
+#define FRF_AA_RX_MAX_PF_LAT_LBN 4
+#define FRF_AA_RX_MAX_PF_LAT_WIDTH 4
+#define FRF_AA_RX_MAX_LU_LAT_LBN 0
+#define FRF_AA_RX_MAX_LU_LAT_WIDTH 4
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_RX_DEBUG_REG(128bit):
+ * undocumented register
+ */
+#define FR_AZ_RX_DEBUG_REG_OFST 0x000008a0
+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AZ_RX_DEBUG_LBN 0
+#define FRF_AZ_RX_DEBUG_WIDTH 64
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_RX_PUSH_DROP_REG(128bit):
+ * Receive descriptor push dropped counter register
+ */
+#define FR_AZ_RX_PUSH_DROP_REG_OFST 0x000008b0
+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AZ_RX_PUSH_DROP_CNT_LBN 0
+#define FRF_AZ_RX_PUSH_DROP_CNT_WIDTH 32
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_CZ_RX_RSS_IPV6_REG1(128bit):
+ * IPv6 RSS Toeplitz hash key low bytes
+ */
+#define FR_CZ_RX_RSS_IPV6_REG1_OFST 0x000008d0
+/* sienaa0=net_func_bar2 */
+
+#define FRF_CZ_RX_RSS_IPV6_TKEY_LO_LBN 0
+#define FRF_CZ_RX_RSS_IPV6_TKEY_LO_WIDTH 128
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_CZ_RX_RSS_IPV6_REG2(128bit):
+ * IPv6 RSS Toeplitz hash key middle bytes
+ */
+#define FR_CZ_RX_RSS_IPV6_REG2_OFST 0x000008e0
+/* sienaa0=net_func_bar2 */
+
+#define FRF_CZ_RX_RSS_IPV6_TKEY_MID_LBN 0
+#define FRF_CZ_RX_RSS_IPV6_TKEY_MID_WIDTH 128
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_CZ_RX_RSS_IPV6_REG3(128bit):
+ * IPv6 RSS Toeplitz hash key upper bytes and IPv6 RSS settings
+ */
+#define FR_CZ_RX_RSS_IPV6_REG3_OFST 0x000008f0
+/* sienaa0=net_func_bar2 */
+
+#define FRF_CZ_RX_RSS_IPV6_THASH_ENABLE_LBN 66
+#define FRF_CZ_RX_RSS_IPV6_THASH_ENABLE_WIDTH 1
+#define FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE_LBN 65
+#define FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE_WIDTH 1
+#define FRF_CZ_RX_RSS_IPV6_TCP_SUPPRESS_LBN 64
+#define FRF_CZ_RX_RSS_IPV6_TCP_SUPPRESS_WIDTH 1
+#define FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN 0
+#define FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH 64
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_TX_FLUSH_DESCQ_REG(128bit):
+ * Transmit flush descriptor queue register
+ */
+#define FR_AZ_TX_FLUSH_DESCQ_REG_OFST 0x00000a00
+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AZ_TX_FLUSH_DESCQ_CMD_LBN 12
+#define FRF_AZ_TX_FLUSH_DESCQ_CMD_WIDTH 1
+#define FRF_AZ_TX_FLUSH_DESCQ_LBN 0
+#define FRF_AZ_TX_FLUSH_DESCQ_WIDTH 12
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_BZ_TX_DESC_UPD_REGP0(128bit):
+ * Transmit descriptor update register.
+ */
+#define FR_BZ_TX_DESC_UPD_REGP0_OFST 0x00000a10
+/* falconb0,sienaa0=net_func_bar2 */
+#define FR_AZ_TX_DESC_UPD_REGP0_STEP 8192
+#define FR_BZ_TX_DESC_UPD_REGP0_ROWS 1024
+/*
+ * FR_AA_TX_DESC_UPD_REG_KER(128bit):
+ * Transmit descriptor update register.
+ */
+#define FR_AA_TX_DESC_UPD_REG_KER_OFST 0x00000a10
+/* falcona0=net_func_bar2 */
+#define FR_AA_TX_DESC_UPD_REG_KER_STEP 8192
+#define FR_AA_TX_DESC_UPD_REG_KER_ROWS 8
+/*
+ * FR_AB_TX_DESC_UPD_REGP123(128bit):
+ * Transmit descriptor update register.
+ */
+#define FR_AB_TX_DESC_UPD_REGP123_OFST 0x01000a10
+/* falconb0=net_func_bar2,falcona0=char_func_bar0 */
+#define FR_AB_TX_DESC_UPD_REGP123_STEP 8192
+#define FR_AB_TX_DESC_UPD_REGP123_ROWS 3072
+/*
+ * FR_AA_TX_DESC_UPD_REGP0(128bit):
+ * Transmit descriptor update register.
+ */
+#define FR_AA_TX_DESC_UPD_REGP0_OFST 0x00008a10
+/* falcona0=char_func_bar0 */
+/* FR_AZ_TX_DESC_UPD_REGP0_STEP 8192 */
+#define FR_AA_TX_DESC_UPD_REGP0_ROWS 1020
+
+#define FRF_AZ_TX_DESC_WPTR_LBN 96
+#define FRF_AZ_TX_DESC_WPTR_WIDTH 12
+#define FRF_AZ_TX_DESC_PUSH_CMD_LBN 95
+#define FRF_AZ_TX_DESC_PUSH_CMD_WIDTH 1
+#define FRF_AZ_TX_DESC_LBN 0
+#define FRF_AZ_TX_DESC_WIDTH 95
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_TX_DC_CFG_REG(128bit):
+ * Transmit descriptor cache configuration register
+ */
+#define FR_AZ_TX_DC_CFG_REG_OFST 0x00000a20
+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AZ_TX_DC_SIZE_LBN 0
+#define FRF_AZ_TX_DC_SIZE_WIDTH 2
+#define FFE_AZ_TX_DC_SIZE_32 2
+#define FFE_AZ_TX_DC_SIZE_16 1
+#define FFE_AZ_TX_DC_SIZE_8 0
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AA_TX_CHKSM_CFG_REG(128bit):
+ * Transmit checksum configuration register
+ */
+#define FR_AA_TX_CHKSM_CFG_REG_OFST 0x00000a30
+/* falcona0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AA_TX_Q_CHKSM_DIS_96_127_LBN 96
+#define FRF_AA_TX_Q_CHKSM_DIS_96_127_WIDTH 32
+#define FRF_AA_TX_Q_CHKSM_DIS_64_95_LBN 64
+#define FRF_AA_TX_Q_CHKSM_DIS_64_95_WIDTH 32
+#define FRF_AA_TX_Q_CHKSM_DIS_32_63_LBN 32
+#define FRF_AA_TX_Q_CHKSM_DIS_32_63_WIDTH 32
+#define FRF_AA_TX_Q_CHKSM_DIS_0_31_LBN 0
+#define FRF_AA_TX_Q_CHKSM_DIS_0_31_WIDTH 32
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_TX_CFG_REG(128bit):
+ * Transmit configuration register
+ */
+#define FR_AZ_TX_CFG_REG_OFST 0x00000a50
+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_CZ_TX_CONT_LOOKUP_THRESH_RANGE_LBN 114
+#define FRF_CZ_TX_CONT_LOOKUP_THRESH_RANGE_WIDTH 8
+#define FRF_CZ_TX_FILTER_TEST_MODE_BIT_LBN 113
+#define FRF_CZ_TX_FILTER_TEST_MODE_BIT_WIDTH 1
+#define FRF_CZ_TX_ETH_FILTER_WILD_SEARCH_RANGE_LBN 105
+#define FRF_CZ_TX_ETH_FILTER_WILD_SEARCH_RANGE_WIDTH 8
+#define FRF_CZ_TX_ETH_FILTER_FULL_SEARCH_RANGE_LBN 97
+#define FRF_CZ_TX_ETH_FILTER_FULL_SEARCH_RANGE_WIDTH 8
+#define FRF_CZ_TX_UDPIP_FILTER_WILD_SEARCH_RANGE_LBN 89
+#define FRF_CZ_TX_UDPIP_FILTER_WILD_SEARCH_RANGE_WIDTH 8
+#define FRF_CZ_TX_UDPIP_FILTER_FULL_SEARCH_RANGE_LBN 81
+#define FRF_CZ_TX_UDPIP_FILTER_FULL_SEARCH_RANGE_WIDTH 8
+#define FRF_CZ_TX_TCPIP_FILTER_WILD_SEARCH_RANGE_LBN 73
+#define FRF_CZ_TX_TCPIP_FILTER_WILD_SEARCH_RANGE_WIDTH 8
+#define FRF_CZ_TX_TCPIP_FILTER_FULL_SEARCH_RANGE_LBN 65
+#define FRF_CZ_TX_TCPIP_FILTER_FULL_SEARCH_RANGE_WIDTH 8
+#define FRF_CZ_TX_FILTER_ALL_VLAN_ETHERTYPES_BIT_LBN 64
+#define FRF_CZ_TX_FILTER_ALL_VLAN_ETHERTYPES_BIT_WIDTH 1
+#define FRF_CZ_TX_VLAN_MATCH_ETHERTYPE_RANGE_LBN 48
+#define FRF_CZ_TX_VLAN_MATCH_ETHERTYPE_RANGE_WIDTH 16
+#define FRF_CZ_TX_FILTER_EN_BIT_LBN 47
+#define FRF_CZ_TX_FILTER_EN_BIT_WIDTH 1
+#define FRF_AZ_TX_IP_ID_P0_OFS_LBN 16
+#define FRF_AZ_TX_IP_ID_P0_OFS_WIDTH 15
+#define FRF_AZ_TX_NO_EOP_DISC_EN_LBN 5
+#define FRF_AZ_TX_NO_EOP_DISC_EN_WIDTH 1
+#define FRF_AZ_TX_P1_PRI_EN_LBN 4
+#define FRF_AZ_TX_P1_PRI_EN_WIDTH 1
+#define FRF_AZ_TX_OWNERR_CTL_LBN 2
+#define FRF_AZ_TX_OWNERR_CTL_WIDTH 1
+#define FRF_AA_TX_NON_IP_DROP_DIS_LBN 1
+#define FRF_AA_TX_NON_IP_DROP_DIS_WIDTH 1
+#define FRF_AZ_TX_IP_ID_REP_EN_LBN 0
+#define FRF_AZ_TX_IP_ID_REP_EN_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_TX_PUSH_DROP_REG(128bit):
+ * Transmit push dropped register
+ */
+#define FR_AZ_TX_PUSH_DROP_REG_OFST 0x00000a60
+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AZ_TX_PUSH_DROP_CNT_LBN 0
+#define FRF_AZ_TX_PUSH_DROP_CNT_WIDTH 32
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_TX_RESERVED_REG(128bit):
+ * Transmit configuration register
+ */
+#define FR_AZ_TX_RESERVED_REG_OFST 0x00000a80
+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AZ_TX_EVT_CNT_LBN 121
+#define FRF_AZ_TX_EVT_CNT_WIDTH 7
+#define FRF_AZ_TX_PREF_AGE_CNT_LBN 119
+#define FRF_AZ_TX_PREF_AGE_CNT_WIDTH 2
+#define FRF_AZ_TX_RD_COMP_TMR_LBN 96
+#define FRF_AZ_TX_RD_COMP_TMR_WIDTH 23
+#define FRF_AZ_TX_PUSH_EN_LBN 89
+#define FRF_AZ_TX_PUSH_EN_WIDTH 1
+#define FRF_AZ_TX_PUSH_CHK_DIS_LBN 88
+#define FRF_AZ_TX_PUSH_CHK_DIS_WIDTH 1
+#define FRF_AZ_TX_D_FF_FULL_P0_LBN 85
+#define FRF_AZ_TX_D_FF_FULL_P0_WIDTH 1
+#define FRF_AZ_TX_DMAR_ST_P0_LBN 81
+#define FRF_AZ_TX_DMAR_ST_P0_WIDTH 1
+#define FRF_AZ_TX_DMAQ_ST_LBN 78
+#define FRF_AZ_TX_DMAQ_ST_WIDTH 1
+#define FRF_AZ_TX_RX_SPACER_LBN 64
+#define FRF_AZ_TX_RX_SPACER_WIDTH 8
+#define FRF_AZ_TX_DROP_ABORT_EN_LBN 60
+#define FRF_AZ_TX_DROP_ABORT_EN_WIDTH 1
+#define FRF_AZ_TX_SOFT_EVT_EN_LBN 59
+#define FRF_AZ_TX_SOFT_EVT_EN_WIDTH 1
+#define FRF_AZ_TX_PS_EVT_DIS_LBN 58
+#define FRF_AZ_TX_PS_EVT_DIS_WIDTH 1
+#define FRF_AZ_TX_RX_SPACER_EN_LBN 57
+#define FRF_AZ_TX_RX_SPACER_EN_WIDTH 1
+#define FRF_AZ_TX_XP_TIMER_LBN 52
+#define FRF_AZ_TX_XP_TIMER_WIDTH 5
+#define FRF_AZ_TX_PREF_SPACER_LBN 44
+#define FRF_AZ_TX_PREF_SPACER_WIDTH 8
+#define FRF_AZ_TX_PREF_WD_TMR_LBN 22
+#define FRF_AZ_TX_PREF_WD_TMR_WIDTH 22
+#define FRF_AZ_TX_ONLY1TAG_LBN 21
+#define FRF_AZ_TX_ONLY1TAG_WIDTH 1
+#define FRF_AZ_TX_PREF_THRESHOLD_LBN 19
+#define FRF_AZ_TX_PREF_THRESHOLD_WIDTH 2
+#define FRF_AZ_TX_ONE_PKT_PER_Q_LBN 18
+#define FRF_AZ_TX_ONE_PKT_PER_Q_WIDTH 1
+#define FRF_AZ_TX_DIS_NON_IP_EV_LBN 17
+#define FRF_AZ_TX_DIS_NON_IP_EV_WIDTH 1
+#define FRF_AA_TX_DMA_FF_THR_LBN 16
+#define FRF_AA_TX_DMA_FF_THR_WIDTH 1
+#define FRF_AZ_TX_DMA_SPACER_LBN 8
+#define FRF_AZ_TX_DMA_SPACER_WIDTH 8
+#define FRF_AA_TX_TCP_DIS_LBN 7
+#define FRF_AA_TX_TCP_DIS_WIDTH 1
+#define FRF_BZ_TX_FLUSH_MIN_LEN_EN_LBN 7
+#define FRF_BZ_TX_FLUSH_MIN_LEN_EN_WIDTH 1
+#define FRF_AA_TX_IP_DIS_LBN 6
+#define FRF_AA_TX_IP_DIS_WIDTH 1
+#define FRF_AZ_TX_MAX_CPL_LBN 2
+#define FRF_AZ_TX_MAX_CPL_WIDTH 2
+#define FFE_AZ_TX_MAX_CPL_16 3
+#define FFE_AZ_TX_MAX_CPL_8 2
+#define FFE_AZ_TX_MAX_CPL_4 1
+#define FFE_AZ_TX_MAX_CPL_NOLIMIT 0
+#define FRF_AZ_TX_MAX_PREF_LBN 0
+#define FRF_AZ_TX_MAX_PREF_WIDTH 2
+#define FFE_AZ_TX_MAX_PREF_32 3
+#define FFE_AZ_TX_MAX_PREF_16 2
+#define FFE_AZ_TX_MAX_PREF_8 1
+#define FFE_AZ_TX_MAX_PREF_OFF 0
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_BZ_TX_PACE_REG(128bit):
+ * Transmit pace control register
+ */
+#define FR_BZ_TX_PACE_REG_OFST 0x00000a90
+/* falconb0,sienaa0=net_func_bar2 */
+/*
+ * FR_AA_TX_PACE_REG(128bit):
+ * Transmit pace control register
+ */
+#define FR_AA_TX_PACE_REG_OFST 0x00f80000
+/* falcona0=char_func_bar0 */
+
+#define FRF_AZ_TX_PACE_SB_NOT_AF_LBN 19
+#define FRF_AZ_TX_PACE_SB_NOT_AF_WIDTH 10
+#define FRF_AZ_TX_PACE_SB_AF_LBN 9
+#define FRF_AZ_TX_PACE_SB_AF_WIDTH 10
+#define FRF_AZ_TX_PACE_FB_BASE_LBN 5
+#define FRF_AZ_TX_PACE_FB_BASE_WIDTH 4
+#define FRF_AZ_TX_PACE_BIN_TH_LBN 0
+#define FRF_AZ_TX_PACE_BIN_TH_WIDTH 5
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_TX_PACE_DROP_QID_REG(128bit):
+ * PACE Drop QID Counter
+ */
+#define FR_AZ_TX_PACE_DROP_QID_REG_OFST 0x00000aa0
+/* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AZ_TX_PACE_QID_DRP_CNT_LBN 0
+#define FRF_AZ_TX_PACE_QID_DRP_CNT_WIDTH 16
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_TX_VLAN_REG(128bit):
+ * Transmit VLAN tag register
+ */
+#define FR_AB_TX_VLAN_REG_OFST 0x00000ae0
+/* falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_TX_VLAN_EN_LBN 127
+#define FRF_AB_TX_VLAN_EN_WIDTH 1
+#define FRF_AB_TX_VLAN7_PORT1_EN_LBN 125
+#define FRF_AB_TX_VLAN7_PORT1_EN_WIDTH 1
+#define FRF_AB_TX_VLAN7_PORT0_EN_LBN 124
+#define FRF_AB_TX_VLAN7_PORT0_EN_WIDTH 1
+#define FRF_AB_TX_VLAN7_LBN 112
+#define FRF_AB_TX_VLAN7_WIDTH 12
+#define FRF_AB_TX_VLAN6_PORT1_EN_LBN 109
+#define FRF_AB_TX_VLAN6_PORT1_EN_WIDTH 1
+#define FRF_AB_TX_VLAN6_PORT0_EN_LBN 108
+#define FRF_AB_TX_VLAN6_PORT0_EN_WIDTH 1
+#define FRF_AB_TX_VLAN6_LBN 96
+#define FRF_AB_TX_VLAN6_WIDTH 12
+#define FRF_AB_TX_VLAN5_PORT1_EN_LBN 93
+#define FRF_AB_TX_VLAN5_PORT1_EN_WIDTH 1
+#define FRF_AB_TX_VLAN5_PORT0_EN_LBN 92
+#define FRF_AB_TX_VLAN5_PORT0_EN_WIDTH 1
+#define FRF_AB_TX_VLAN5_LBN 80
+#define FRF_AB_TX_VLAN5_WIDTH 12
+#define FRF_AB_TX_VLAN4_PORT1_EN_LBN 77
+#define FRF_AB_TX_VLAN4_PORT1_EN_WIDTH 1
+#define FRF_AB_TX_VLAN4_PORT0_EN_LBN 76
+#define FRF_AB_TX_VLAN4_PORT0_EN_WIDTH 1
+#define FRF_AB_TX_VLAN4_LBN 64
+#define FRF_AB_TX_VLAN4_WIDTH 12
+#define FRF_AB_TX_VLAN3_PORT1_EN_LBN 61
+#define FRF_AB_TX_VLAN3_PORT1_EN_WIDTH 1
+#define FRF_AB_TX_VLAN3_PORT0_EN_LBN 60
+#define FRF_AB_TX_VLAN3_PORT0_EN_WIDTH 1
+#define FRF_AB_TX_VLAN3_LBN 48
+#define FRF_AB_TX_VLAN3_WIDTH 12
+#define FRF_AB_TX_VLAN2_PORT1_EN_LBN 45
+#define FRF_AB_TX_VLAN2_PORT1_EN_WIDTH 1
+#define FRF_AB_TX_VLAN2_PORT0_EN_LBN 44
+#define FRF_AB_TX_VLAN2_PORT0_EN_WIDTH 1
+#define FRF_AB_TX_VLAN2_LBN 32
+#define FRF_AB_TX_VLAN2_WIDTH 12
+#define FRF_AB_TX_VLAN1_PORT1_EN_LBN 29
+#define FRF_AB_TX_VLAN1_PORT1_EN_WIDTH 1
+#define FRF_AB_TX_VLAN1_PORT0_EN_LBN 28
+#define FRF_AB_TX_VLAN1_PORT0_EN_WIDTH 1
+#define FRF_AB_TX_VLAN1_LBN 16
+#define FRF_AB_TX_VLAN1_WIDTH 12
+#define FRF_AB_TX_VLAN0_PORT1_EN_LBN 13
+#define FRF_AB_TX_VLAN0_PORT1_EN_WIDTH 1
+#define FRF_AB_TX_VLAN0_PORT0_EN_LBN 12
+#define FRF_AB_TX_VLAN0_PORT0_EN_WIDTH 1
+#define FRF_AB_TX_VLAN0_LBN 0
+#define FRF_AB_TX_VLAN0_WIDTH 12
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_TX_IPFIL_PORTEN_REG(128bit):
+ * Transmit filter control register
+ */
+#define FR_AZ_TX_IPFIL_PORTEN_REG_OFST 0x00000af0
+/* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AZ_TX_MADR0_FIL_EN_LBN 64
+#define FRF_AZ_TX_MADR0_FIL_EN_WIDTH 1
+#define FRF_AB_TX_IPFIL31_PORT_EN_LBN 62
+#define FRF_AB_TX_IPFIL31_PORT_EN_WIDTH 1
+#define FRF_AB_TX_IPFIL30_PORT_EN_LBN 60
+#define FRF_AB_TX_IPFIL30_PORT_EN_WIDTH 1
+#define FRF_AB_TX_IPFIL29_PORT_EN_LBN 58
+#define FRF_AB_TX_IPFIL29_PORT_EN_WIDTH 1
+#define FRF_AB_TX_IPFIL28_PORT_EN_LBN 56
+#define FRF_AB_TX_IPFIL28_PORT_EN_WIDTH 1
+#define FRF_AB_TX_IPFIL27_PORT_EN_LBN 54
+#define FRF_AB_TX_IPFIL27_PORT_EN_WIDTH 1
+#define FRF_AB_TX_IPFIL26_PORT_EN_LBN 52
+#define FRF_AB_TX_IPFIL26_PORT_EN_WIDTH 1
+#define FRF_AB_TX_IPFIL25_PORT_EN_LBN 50
+#define FRF_AB_TX_IPFIL25_PORT_EN_WIDTH 1
+#define FRF_AB_TX_IPFIL24_PORT_EN_LBN 48
+#define FRF_AB_TX_IPFIL24_PORT_EN_WIDTH 1
+#define FRF_AB_TX_IPFIL23_PORT_EN_LBN 46
+#define FRF_AB_TX_IPFIL23_PORT_EN_WIDTH 1
+#define FRF_AB_TX_IPFIL22_PORT_EN_LBN 44
+#define FRF_AB_TX_IPFIL22_PORT_EN_WIDTH 1
+#define FRF_AB_TX_IPFIL21_PORT_EN_LBN 42
+#define FRF_AB_TX_IPFIL21_PORT_EN_WIDTH 1
+#define FRF_AB_TX_IPFIL20_PORT_EN_LBN 40
+#define FRF_AB_TX_IPFIL20_PORT_EN_WIDTH 1
+#define FRF_AB_TX_IPFIL19_PORT_EN_LBN 38
+#define FRF_AB_TX_IPFIL19_PORT_EN_WIDTH 1
+#define FRF_AB_TX_IPFIL18_PORT_EN_LBN 36
+#define FRF_AB_TX_IPFIL18_PORT_EN_WIDTH 1
+#define FRF_AB_TX_IPFIL17_PORT_EN_LBN 34
+#define FRF_AB_TX_IPFIL17_PORT_EN_WIDTH 1
+#define FRF_AB_TX_IPFIL16_PORT_EN_LBN 32
+#define FRF_AB_TX_IPFIL16_PORT_EN_WIDTH 1
+#define FRF_AB_TX_IPFIL15_PORT_EN_LBN 30
+#define FRF_AB_TX_IPFIL15_PORT_EN_WIDTH 1
+#define FRF_AB_TX_IPFIL14_PORT_EN_LBN 28
+#define FRF_AB_TX_IPFIL14_PORT_EN_WIDTH 1
+#define FRF_AB_TX_IPFIL13_PORT_EN_LBN 26
+#define FRF_AB_TX_IPFIL13_PORT_EN_WIDTH 1
+#define FRF_AB_TX_IPFIL12_PORT_EN_LBN 24
+#define FRF_AB_TX_IPFIL12_PORT_EN_WIDTH 1
+#define FRF_AB_TX_IPFIL11_PORT_EN_LBN 22
+#define FRF_AB_TX_IPFIL11_PORT_EN_WIDTH 1
+#define FRF_AB_TX_IPFIL10_PORT_EN_LBN 20
+#define FRF_AB_TX_IPFIL10_PORT_EN_WIDTH 1
+#define FRF_AB_TX_IPFIL9_PORT_EN_LBN 18
+#define FRF_AB_TX_IPFIL9_PORT_EN_WIDTH 1
+#define FRF_AB_TX_IPFIL8_PORT_EN_LBN 16
+#define FRF_AB_TX_IPFIL8_PORT_EN_WIDTH 1
+#define FRF_AB_TX_IPFIL7_PORT_EN_LBN 14
+#define FRF_AB_TX_IPFIL7_PORT_EN_WIDTH 1
+#define FRF_AB_TX_IPFIL6_PORT_EN_LBN 12
+#define FRF_AB_TX_IPFIL6_PORT_EN_WIDTH 1
+#define FRF_AB_TX_IPFIL5_PORT_EN_LBN 10
+#define FRF_AB_TX_IPFIL5_PORT_EN_WIDTH 1
+#define FRF_AB_TX_IPFIL4_PORT_EN_LBN 8
+#define FRF_AB_TX_IPFIL4_PORT_EN_WIDTH 1
+#define FRF_AB_TX_IPFIL3_PORT_EN_LBN 6
+#define FRF_AB_TX_IPFIL3_PORT_EN_WIDTH 1
+#define FRF_AB_TX_IPFIL2_PORT_EN_LBN 4
+#define FRF_AB_TX_IPFIL2_PORT_EN_WIDTH 1
+#define FRF_AB_TX_IPFIL1_PORT_EN_LBN 2
+#define FRF_AB_TX_IPFIL1_PORT_EN_WIDTH 1
+#define FRF_AB_TX_IPFIL0_PORT_EN_LBN 0
+#define FRF_AB_TX_IPFIL0_PORT_EN_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_TX_IPFIL_TBL(128bit):
+ * Transmit IP source address filter table
+ */
+#define FR_AB_TX_IPFIL_TBL_OFST 0x00000b00
+/* falconb0=net_func_bar2,falcona0=char_func_bar0 */
+#define FR_AB_TX_IPFIL_TBL_STEP 16
+#define FR_AB_TX_IPFIL_TBL_ROWS 16
+
+#define FRF_AB_TX_IPFIL_MASK_1_LBN 96
+#define FRF_AB_TX_IPFIL_MASK_1_WIDTH 32
+#define FRF_AB_TX_IP_SRC_ADR_1_LBN 64
+#define FRF_AB_TX_IP_SRC_ADR_1_WIDTH 32
+#define FRF_AB_TX_IPFIL_MASK_0_LBN 32
+#define FRF_AB_TX_IPFIL_MASK_0_WIDTH 32
+#define FRF_AB_TX_IP_SRC_ADR_0_LBN 0
+#define FRF_AB_TX_IP_SRC_ADR_0_WIDTH 32
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_BB_TX_SRC_MAC_TBL(128bit):
+ * Transmit IP source address filter table
+ */
+#define FR_BB_TX_SRC_MAC_TBL_OFST 0x00001000
+/* falconb0=net_func_bar2 */
+#define FR_BB_TX_SRC_MAC_TBL_STEP 16
+#define FR_BB_TX_SRC_MAC_TBL_ROWS 16
+
+#define FRF_BB_TX_SRC_MAC_ADR_1_LBN 64
+#define FRF_BB_TX_SRC_MAC_ADR_1_WIDTH 48
+#define FRF_BB_TX_SRC_MAC_ADR_0_LBN 0
+#define FRF_BB_TX_SRC_MAC_ADR_0_WIDTH 48
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_BB_TX_SRC_MAC_CTL_REG(128bit):
+ * Transmit MAC source address filter control
+ */
+#define FR_BB_TX_SRC_MAC_CTL_REG_OFST 0x00001100
+/* falconb0=net_func_bar2 */
+
+#define FRF_BB_TX_SRC_DROP_CTR_LBN 16
+#define FRF_BB_TX_SRC_DROP_CTR_WIDTH 16
+#define FRF_BB_TX_SRC_FLTR_EN_LBN 15
+#define FRF_BB_TX_SRC_FLTR_EN_WIDTH 1
+#define FRF_BB_TX_DROP_CTR_CLR_LBN 12
+#define FRF_BB_TX_DROP_CTR_CLR_WIDTH 1
+#define FRF_BB_TX_MAC_QID_SEL_LBN 0
+#define FRF_BB_TX_MAC_QID_SEL_WIDTH 3
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AA_RX_DESC_PTR_TBL_KER(128bit):
+ * Receive descriptor pointer table
+ */
+#define FR_AA_RX_DESC_PTR_TBL_KER_OFST 0x00011800
+/* falcona0=net_func_bar2 */
+#define FR_AA_RX_DESC_PTR_TBL_KER_STEP 16
+#define FR_AA_RX_DESC_PTR_TBL_KER_ROWS 4
+/*
+ * FR_AZ_RX_DESC_PTR_TBL(128bit):
+ * Receive descriptor pointer table
+ */
+#define FR_AZ_RX_DESC_PTR_TBL_OFST 0x00f40000
+/* falconb0=net_func_bar2,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
+#define FR_AZ_RX_DESC_PTR_TBL_STEP 16
+#define FR_AB_RX_DESC_PTR_TBL_ROWS 4096
+#define FR_CZ_RX_DESC_PTR_TBL_ROWS 1024
+
+#define FRF_CZ_RX_HDR_SPLIT_LBN 90
+#define FRF_CZ_RX_HDR_SPLIT_WIDTH 1
+#define FRF_AA_RX_RESET_LBN 89
+#define FRF_AA_RX_RESET_WIDTH 1
+#define FRF_AZ_RX_ISCSI_DDIG_EN_LBN 88
+#define FRF_AZ_RX_ISCSI_DDIG_EN_WIDTH 1
+#define FRF_AZ_RX_ISCSI_HDIG_EN_LBN 87
+#define FRF_AZ_RX_ISCSI_HDIG_EN_WIDTH 1
+#define FRF_AZ_RX_DESC_PREF_ACT_LBN 86
+#define FRF_AZ_RX_DESC_PREF_ACT_WIDTH 1
+#define FRF_AZ_RX_DC_HW_RPTR_LBN 80
+#define FRF_AZ_RX_DC_HW_RPTR_WIDTH 6
+#define FRF_AZ_RX_DESCQ_HW_RPTR_LBN 68
+#define FRF_AZ_RX_DESCQ_HW_RPTR_WIDTH 12
+#define FRF_AZ_RX_DESCQ_SW_WPTR_LBN 56
+#define FRF_AZ_RX_DESCQ_SW_WPTR_WIDTH 12
+#define FRF_AZ_RX_DESCQ_BUF_BASE_ID_LBN 36
+#define FRF_AZ_RX_DESCQ_BUF_BASE_ID_WIDTH 20
+#define FRF_AZ_RX_DESCQ_EVQ_ID_LBN 24
+#define FRF_AZ_RX_DESCQ_EVQ_ID_WIDTH 12
+#define FRF_AZ_RX_DESCQ_OWNER_ID_LBN 10
+#define FRF_AZ_RX_DESCQ_OWNER_ID_WIDTH 14
+#define FRF_AZ_RX_DESCQ_LABEL_LBN 5
+#define FRF_AZ_RX_DESCQ_LABEL_WIDTH 5
+#define FRF_AZ_RX_DESCQ_SIZE_LBN 3
+#define FRF_AZ_RX_DESCQ_SIZE_WIDTH 2
+#define FFE_AZ_RX_DESCQ_SIZE_4K 3
+#define FFE_AZ_RX_DESCQ_SIZE_2K 2
+#define FFE_AZ_RX_DESCQ_SIZE_1K 1
+#define FFE_AZ_RX_DESCQ_SIZE_512 0
+#define FRF_AZ_RX_DESCQ_TYPE_LBN 2
+#define FRF_AZ_RX_DESCQ_TYPE_WIDTH 1
+#define FRF_AZ_RX_DESCQ_JUMBO_LBN 1
+#define FRF_AZ_RX_DESCQ_JUMBO_WIDTH 1
+#define FRF_AZ_RX_DESCQ_EN_LBN 0
+#define FRF_AZ_RX_DESCQ_EN_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AA_TX_DESC_PTR_TBL_KER(128bit):
+ * Transmit descriptor pointer
+ */
+#define FR_AA_TX_DESC_PTR_TBL_KER_OFST 0x00011900
+/* falcona0=net_func_bar2 */
+#define FR_AA_TX_DESC_PTR_TBL_KER_STEP 16
+#define FR_AA_TX_DESC_PTR_TBL_KER_ROWS 8
+/*
+ * FR_AZ_TX_DESC_PTR_TBL(128bit):
+ * Transmit descriptor pointer
+ */
+#define FR_AZ_TX_DESC_PTR_TBL_OFST 0x00f50000
+/* falconb0=net_func_bar2,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
+#define FR_AZ_TX_DESC_PTR_TBL_STEP 16
+#define FR_AB_TX_DESC_PTR_TBL_ROWS 4096
+#define FR_CZ_TX_DESC_PTR_TBL_ROWS 1024
+
+#define FRF_CZ_TX_DPT_Q_MASK_WIDTH_LBN 94
+#define FRF_CZ_TX_DPT_Q_MASK_WIDTH_WIDTH 2
+#define FRF_CZ_TX_DPT_ETH_FILT_EN_LBN 93
+#define FRF_CZ_TX_DPT_ETH_FILT_EN_WIDTH 1
+#define FRF_CZ_TX_DPT_IP_FILT_EN_LBN 92
+#define FRF_CZ_TX_DPT_IP_FILT_EN_WIDTH 1
+#define FRF_BZ_TX_NON_IP_DROP_DIS_LBN 91
+#define FRF_BZ_TX_NON_IP_DROP_DIS_WIDTH 1
+#define FRF_BZ_TX_IP_CHKSM_DIS_LBN 90
+#define FRF_BZ_TX_IP_CHKSM_DIS_WIDTH 1
+#define FRF_BZ_TX_TCP_CHKSM_DIS_LBN 89
+#define FRF_BZ_TX_TCP_CHKSM_DIS_WIDTH 1
+#define FRF_AZ_TX_DESCQ_EN_LBN 88
+#define FRF_AZ_TX_DESCQ_EN_WIDTH 1
+#define FRF_AZ_TX_ISCSI_DDIG_EN_LBN 87
+#define FRF_AZ_TX_ISCSI_DDIG_EN_WIDTH 1
+#define FRF_AZ_TX_ISCSI_HDIG_EN_LBN 86
+#define FRF_AZ_TX_ISCSI_HDIG_EN_WIDTH 1
+#define FRF_AZ_TX_DC_HW_RPTR_LBN 80
+#define FRF_AZ_TX_DC_HW_RPTR_WIDTH 6
+#define FRF_AZ_TX_DESCQ_HW_RPTR_LBN 68
+#define FRF_AZ_TX_DESCQ_HW_RPTR_WIDTH 12
+#define FRF_AZ_TX_DESCQ_SW_WPTR_LBN 56
+#define FRF_AZ_TX_DESCQ_SW_WPTR_WIDTH 12
+#define FRF_AZ_TX_DESCQ_BUF_BASE_ID_LBN 36
+#define FRF_AZ_TX_DESCQ_BUF_BASE_ID_WIDTH 20
+#define FRF_AZ_TX_DESCQ_EVQ_ID_LBN 24
+#define FRF_AZ_TX_DESCQ_EVQ_ID_WIDTH 12
+#define FRF_AZ_TX_DESCQ_OWNER_ID_LBN 10
+#define FRF_AZ_TX_DESCQ_OWNER_ID_WIDTH 14
+#define FRF_AZ_TX_DESCQ_LABEL_LBN 5
+#define FRF_AZ_TX_DESCQ_LABEL_WIDTH 5
+#define FRF_AZ_TX_DESCQ_SIZE_LBN 3
+#define FRF_AZ_TX_DESCQ_SIZE_WIDTH 2
+#define FFE_AZ_TX_DESCQ_SIZE_4K 3
+#define FFE_AZ_TX_DESCQ_SIZE_2K 2
+#define FFE_AZ_TX_DESCQ_SIZE_1K 1
+#define FFE_AZ_TX_DESCQ_SIZE_512 0
+#define FRF_AZ_TX_DESCQ_TYPE_LBN 1
+#define FRF_AZ_TX_DESCQ_TYPE_WIDTH 2
+#define FRF_AZ_TX_DESCQ_FLUSH_LBN 0
+#define FRF_AZ_TX_DESCQ_FLUSH_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AA_EVQ_PTR_TBL_KER(128bit):
+ * Event queue pointer table
+ */
+#define FR_AA_EVQ_PTR_TBL_KER_OFST 0x00011a00
+/* falcona0=net_func_bar2 */
+#define FR_AA_EVQ_PTR_TBL_KER_STEP 16
+#define FR_AA_EVQ_PTR_TBL_KER_ROWS 4
+/*
+ * FR_AZ_EVQ_PTR_TBL(128bit):
+ * Event queue pointer table
+ */
+#define FR_AZ_EVQ_PTR_TBL_OFST 0x00f60000
+/* sienaa0=net_func_bar2,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+#define FR_AZ_EVQ_PTR_TBL_STEP 16
+#define FR_CZ_EVQ_PTR_TBL_ROWS 1024
+#define FR_AB_EVQ_PTR_TBL_ROWS 4096
+
+#define FRF_BZ_EVQ_RPTR_IGN_LBN 40
+#define FRF_BZ_EVQ_RPTR_IGN_WIDTH 1
+#define FRF_AB_EVQ_WKUP_OR_INT_EN_LBN 39
+#define FRF_AB_EVQ_WKUP_OR_INT_EN_WIDTH 1
+#define FRF_CZ_EVQ_DOS_PROTECT_EN_LBN 39
+#define FRF_CZ_EVQ_DOS_PROTECT_EN_WIDTH 1
+#define FRF_AZ_EVQ_NXT_WPTR_LBN 24
+#define FRF_AZ_EVQ_NXT_WPTR_WIDTH 15
+#define FRF_AZ_EVQ_EN_LBN 23
+#define FRF_AZ_EVQ_EN_WIDTH 1
+#define FRF_AZ_EVQ_SIZE_LBN 20
+#define FRF_AZ_EVQ_SIZE_WIDTH 3
+#define FFE_AZ_EVQ_SIZE_32K 6
+#define FFE_AZ_EVQ_SIZE_16K 5
+#define FFE_AZ_EVQ_SIZE_8K 4
+#define FFE_AZ_EVQ_SIZE_4K 3
+#define FFE_AZ_EVQ_SIZE_2K 2
+#define FFE_AZ_EVQ_SIZE_1K 1
+#define FFE_AZ_EVQ_SIZE_512 0
+#define FRF_AZ_EVQ_BUF_BASE_ID_LBN 0
+#define FRF_AZ_EVQ_BUF_BASE_ID_WIDTH 20
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AA_BUF_HALF_TBL_KER(64bit):
+ * Buffer table in half buffer table mode direct access by driver
+ */
+#define FR_AA_BUF_HALF_TBL_KER_OFST 0x00018000
+/* falcona0=net_func_bar2 */
+#define FR_AA_BUF_HALF_TBL_KER_STEP 8
+#define FR_AA_BUF_HALF_TBL_KER_ROWS 4096
+/*
+ * FR_AZ_BUF_HALF_TBL(64bit):
+ * Buffer table in half buffer table mode direct access by driver
+ */
+#define FR_AZ_BUF_HALF_TBL_OFST 0x00800000
+/* sienaa0=net_func_bar2,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+#define FR_AZ_BUF_HALF_TBL_STEP 8
+#define FR_CZ_BUF_HALF_TBL_ROWS 147456
+#define FR_AB_BUF_HALF_TBL_ROWS 524288
+
+#define FRF_AZ_BUF_ADR_HBUF_ODD_LBN 44
+#define FRF_AZ_BUF_ADR_HBUF_ODD_WIDTH 20
+#define FRF_AZ_BUF_OWNER_ID_HBUF_ODD_LBN 32
+#define FRF_AZ_BUF_OWNER_ID_HBUF_ODD_WIDTH 12
+#define FRF_AZ_BUF_ADR_HBUF_EVEN_LBN 12
+#define FRF_AZ_BUF_ADR_HBUF_EVEN_WIDTH 20
+#define FRF_AZ_BUF_OWNER_ID_HBUF_EVEN_LBN 0
+#define FRF_AZ_BUF_OWNER_ID_HBUF_EVEN_WIDTH 12
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AA_BUF_FULL_TBL_KER(64bit):
+ * Buffer table in full buffer table mode direct access by driver
+ */
+#define FR_AA_BUF_FULL_TBL_KER_OFST 0x00018000
+/* falcona0=net_func_bar2 */
+#define FR_AA_BUF_FULL_TBL_KER_STEP 8
+#define FR_AA_BUF_FULL_TBL_KER_ROWS 4096
+/*
+ * FR_AZ_BUF_FULL_TBL(64bit):
+ * Buffer table in full buffer table mode direct access by driver
+ */
+#define FR_AZ_BUF_FULL_TBL_OFST 0x00800000
+/* sienaa0=net_func_bar2,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+#define FR_AZ_BUF_FULL_TBL_STEP 8
+#define FR_CZ_BUF_FULL_TBL_ROWS 147456
+#define FR_AB_BUF_FULL_TBL_ROWS 917504
+
+#define FRF_AZ_BUF_FULL_UNUSED_LBN 51
+#define FRF_AZ_BUF_FULL_UNUSED_WIDTH 13
+#define FRF_AZ_IP_DAT_BUF_SIZE_LBN 50
+#define FRF_AZ_IP_DAT_BUF_SIZE_WIDTH 1
+#define FRF_AZ_BUF_ADR_REGION_LBN 48
+#define FRF_AZ_BUF_ADR_REGION_WIDTH 2
+#define FFE_AZ_BUF_ADR_REGN3 3
+#define FFE_AZ_BUF_ADR_REGN2 2
+#define FFE_AZ_BUF_ADR_REGN1 1
+#define FFE_AZ_BUF_ADR_REGN0 0
+#define FRF_AZ_BUF_ADR_FBUF_LBN 14
+#define FRF_AZ_BUF_ADR_FBUF_WIDTH 34
+#define FRF_AZ_BUF_OWNER_ID_FBUF_LBN 0
+#define FRF_AZ_BUF_OWNER_ID_FBUF_WIDTH 14
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_RX_FILTER_TBL0(128bit):
+ * TCP/IPv4 Receive filter table
+ */
+#define FR_AZ_RX_FILTER_TBL0_OFST 0x00f00000
+/* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
+#define FR_AZ_RX_FILTER_TBL0_STEP 32
+#define FR_AZ_RX_FILTER_TBL0_ROWS 8192
+/*
+ * FR_AB_RX_FILTER_TBL1(128bit):
+ * TCP/IPv4 Receive filter table
+ */
+#define FR_AB_RX_FILTER_TBL1_OFST 0x00f00010
+/* falconb0=net_func_bar2,falcona0=char_func_bar0 */
+#define FR_AB_RX_FILTER_TBL1_STEP 32
+#define FR_AB_RX_FILTER_TBL1_ROWS 8192
+
+#define FRF_BZ_RSS_EN_LBN 110
+#define FRF_BZ_RSS_EN_WIDTH 1
+#define FRF_BZ_SCATTER_EN_LBN 109
+#define FRF_BZ_SCATTER_EN_WIDTH 1
+#define FRF_AZ_TCP_UDP_LBN 108
+#define FRF_AZ_TCP_UDP_WIDTH 1
+#define FRF_AZ_RXQ_ID_LBN 96
+#define FRF_AZ_RXQ_ID_WIDTH 12
+#define FRF_AZ_DEST_IP_LBN 64
+#define FRF_AZ_DEST_IP_WIDTH 32
+#define FRF_AZ_DEST_PORT_TCP_LBN 48
+#define FRF_AZ_DEST_PORT_TCP_WIDTH 16
+#define FRF_AZ_SRC_IP_LBN 16
+#define FRF_AZ_SRC_IP_WIDTH 32
+#define FRF_AZ_SRC_TCP_DEST_UDP_LBN 0
+#define FRF_AZ_SRC_TCP_DEST_UDP_WIDTH 16
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_CZ_RX_MAC_FILTER_TBL0(128bit):
+ * Receive Ethernet filter table
+ */
+#define FR_CZ_RX_MAC_FILTER_TBL0_OFST 0x00f00010
+/* sienaa0=net_func_bar2 */
+#define FR_CZ_RX_MAC_FILTER_TBL0_STEP 32
+#define FR_CZ_RX_MAC_FILTER_TBL0_ROWS 512
+
+#define FRF_CZ_RMFT_RSS_EN_LBN 75
+#define FRF_CZ_RMFT_RSS_EN_WIDTH 1
+#define FRF_CZ_RMFT_SCATTER_EN_LBN 74
+#define FRF_CZ_RMFT_SCATTER_EN_WIDTH 1
+#define FRF_CZ_RMFT_IP_OVERRIDE_LBN 73
+#define FRF_CZ_RMFT_IP_OVERRIDE_WIDTH 1
+#define FRF_CZ_RMFT_RXQ_ID_LBN 61
+#define FRF_CZ_RMFT_RXQ_ID_WIDTH 12
+#define FRF_CZ_RMFT_WILDCARD_MATCH_LBN 60
+#define FRF_CZ_RMFT_WILDCARD_MATCH_WIDTH 1
+#define FRF_CZ_RMFT_DEST_MAC_LBN 16
+#define FRF_CZ_RMFT_DEST_MAC_WIDTH 44
+#define FRF_CZ_RMFT_VLAN_ID_LBN 0
+#define FRF_CZ_RMFT_VLAN_ID_WIDTH 12
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_TIMER_TBL(128bit):
+ * Timer table
+ */
+#define FR_AZ_TIMER_TBL_OFST 0x00f70000
+/* sienaa0=net_func_bar2,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+#define FR_AZ_TIMER_TBL_STEP 16
+#define FR_CZ_TIMER_TBL_ROWS 1024
+#define FR_AB_TIMER_TBL_ROWS 4096
+
+#define FRF_CZ_TIMER_Q_EN_LBN 33
+#define FRF_CZ_TIMER_Q_EN_WIDTH 1
+#define FRF_CZ_INT_ARMD_LBN 32
+#define FRF_CZ_INT_ARMD_WIDTH 1
+#define FRF_CZ_INT_PEND_LBN 31
+#define FRF_CZ_INT_PEND_WIDTH 1
+#define FRF_CZ_HOST_NOTIFY_MODE_LBN 30
+#define FRF_CZ_HOST_NOTIFY_MODE_WIDTH 1
+#define FRF_CZ_RELOAD_TIMER_VAL_LBN 16
+#define FRF_CZ_RELOAD_TIMER_VAL_WIDTH 14
+#define FRF_CZ_TIMER_MODE_LBN 14
+#define FRF_CZ_TIMER_MODE_WIDTH 2
+#define FFE_CZ_TIMER_MODE_INT_HLDOFF 3
+#define FFE_CZ_TIMER_MODE_TRIG_START 2
+#define FFE_CZ_TIMER_MODE_IMMED_START 1
+#define FFE_CZ_TIMER_MODE_DIS 0
+#define FRF_AB_TIMER_MODE_LBN 12
+#define FRF_AB_TIMER_MODE_WIDTH 2
+#define FFE_AB_TIMER_MODE_INT_HLDOFF 2
+#define FFE_AB_TIMER_MODE_TRIG_START 2
+#define FFE_AB_TIMER_MODE_IMMED_START 1
+#define FFE_AB_TIMER_MODE_DIS 0
+#define FRF_CZ_TIMER_VAL_LBN 0
+#define FRF_CZ_TIMER_VAL_WIDTH 14
+#define FRF_AB_TIMER_VAL_LBN 0
+#define FRF_AB_TIMER_VAL_WIDTH 12
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_BZ_TX_PACE_TBL(128bit):
+ * Transmit pacing table
+ */
+#define FR_BZ_TX_PACE_TBL_OFST 0x00f80000
+/* sienaa0=net_func_bar2,falconb0=net_func_bar2 */
+#define FR_AZ_TX_PACE_TBL_STEP 16
+#define FR_CZ_TX_PACE_TBL_ROWS 1024
+#define FR_BB_TX_PACE_TBL_ROWS 4096
+/*
+ * FR_AA_TX_PACE_TBL(128bit):
+ * Transmit pacing table
+ */
+#define FR_AA_TX_PACE_TBL_OFST 0x00f80040
+/* falcona0=char_func_bar0 */
+/* FR_AZ_TX_PACE_TBL_STEP 16 */
+#define FR_AA_TX_PACE_TBL_ROWS 4092
+
+#define FRF_AZ_TX_PACE_LBN 0
+#define FRF_AZ_TX_PACE_WIDTH 5
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_BZ_RX_INDIRECTION_TBL(7bit):
+ * RX Indirection Table
+ */
+#define FR_BZ_RX_INDIRECTION_TBL_OFST 0x00fb0000
+/* falconb0,sienaa0=net_func_bar2 */
+#define FR_BZ_RX_INDIRECTION_TBL_STEP 16
+#define FR_BZ_RX_INDIRECTION_TBL_ROWS 128
+
+#define FRF_BZ_IT_QUEUE_LBN 0
+#define FRF_BZ_IT_QUEUE_WIDTH 6
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_CZ_TX_FILTER_TBL0(128bit):
+ * TCP/IPv4 Transmit filter table
+ */
+#define FR_CZ_TX_FILTER_TBL0_OFST 0x00fc0000
+/* sienaa0=net_func_bar2 */
+#define FR_CZ_TX_FILTER_TBL0_STEP 16
+#define FR_CZ_TX_FILTER_TBL0_ROWS 8192
+
+#define FRF_CZ_TIFT_TCP_UDP_LBN 108
+#define FRF_CZ_TIFT_TCP_UDP_WIDTH 1
+#define FRF_CZ_TIFT_TXQ_ID_LBN 96
+#define FRF_CZ_TIFT_TXQ_ID_WIDTH 12
+#define FRF_CZ_TIFT_DEST_IP_LBN 64
+#define FRF_CZ_TIFT_DEST_IP_WIDTH 32
+#define FRF_CZ_TIFT_DEST_PORT_TCP_LBN 48
+#define FRF_CZ_TIFT_DEST_PORT_TCP_WIDTH 16
+#define FRF_CZ_TIFT_SRC_IP_LBN 16
+#define FRF_CZ_TIFT_SRC_IP_WIDTH 32
+#define FRF_CZ_TIFT_SRC_TCP_DEST_UDP_LBN 0
+#define FRF_CZ_TIFT_SRC_TCP_DEST_UDP_WIDTH 16
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_CZ_TX_MAC_FILTER_TBL0(128bit):
+ * Transmit Ethernet filter table
+ */
+#define FR_CZ_TX_MAC_FILTER_TBL0_OFST 0x00fe0000
+/* sienaa0=net_func_bar2 */
+#define FR_CZ_TX_MAC_FILTER_TBL0_STEP 16
+#define FR_CZ_TX_MAC_FILTER_TBL0_ROWS 512
+
+#define FRF_CZ_TMFT_TXQ_ID_LBN 61
+#define FRF_CZ_TMFT_TXQ_ID_WIDTH 12
+#define FRF_CZ_TMFT_WILDCARD_MATCH_LBN 60
+#define FRF_CZ_TMFT_WILDCARD_MATCH_WIDTH 1
+#define FRF_CZ_TMFT_SRC_MAC_LBN 16
+#define FRF_CZ_TMFT_SRC_MAC_WIDTH 44
+#define FRF_CZ_TMFT_VLAN_ID_LBN 0
+#define FRF_CZ_TMFT_VLAN_ID_WIDTH 12
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_CZ_MC_TREG_SMEM(32bit):
+ * MC Shared Memory
+ */
+#define FR_CZ_MC_TREG_SMEM_OFST 0x00ff0000
+/* sienaa0=net_func_bar2 */
+#define FR_CZ_MC_TREG_SMEM_STEP 4
+#define FR_CZ_MC_TREG_SMEM_ROWS 512
+
+#define FRF_CZ_MC_TREG_SMEM_ROW_LBN 0
+#define FRF_CZ_MC_TREG_SMEM_ROW_WIDTH 32
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_BB_MSIX_VECTOR_TABLE(128bit):
+ * MSIX Vector Table
+ */
+#define FR_BB_MSIX_VECTOR_TABLE_OFST 0x00ff0000
+/* falconb0=net_func_bar2 */
+#define FR_BZ_MSIX_VECTOR_TABLE_STEP 16
+#define FR_BB_MSIX_VECTOR_TABLE_ROWS 64
+/*
+ * FR_CZ_MSIX_VECTOR_TABLE(128bit):
+ * MSIX Vector Table
+ */
+#define FR_CZ_MSIX_VECTOR_TABLE_OFST 0x00000000
+/* sienaa0=pci_f0_bar4 */
+/* FR_BZ_MSIX_VECTOR_TABLE_STEP 16 */
+#define FR_CZ_MSIX_VECTOR_TABLE_ROWS 1024
+
+#define FRF_BZ_MSIX_VECTOR_RESERVED_LBN 97
+#define FRF_BZ_MSIX_VECTOR_RESERVED_WIDTH 31
+#define FRF_BZ_MSIX_VECTOR_MASK_LBN 96
+#define FRF_BZ_MSIX_VECTOR_MASK_WIDTH 1
+#define FRF_BZ_MSIX_MESSAGE_DATA_LBN 64
+#define FRF_BZ_MSIX_MESSAGE_DATA_WIDTH 32
+#define FRF_BZ_MSIX_MESSAGE_ADDRESS_HI_LBN 32
+#define FRF_BZ_MSIX_MESSAGE_ADDRESS_HI_WIDTH 32
+#define FRF_BZ_MSIX_MESSAGE_ADDRESS_LO_LBN 0
+#define FRF_BZ_MSIX_MESSAGE_ADDRESS_LO_WIDTH 32
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_BB_MSIX_PBA_TABLE(32bit):
+ * MSIX Pending Bit Array
+ */
+#define FR_BB_MSIX_PBA_TABLE_OFST 0x00ff2000
+/* falconb0=net_func_bar2 */
+#define FR_BZ_MSIX_PBA_TABLE_STEP 4
+#define FR_BB_MSIX_PBA_TABLE_ROWS 2
+/*
+ * FR_CZ_MSIX_PBA_TABLE(32bit):
+ * MSIX Pending Bit Array
+ */
+#define FR_CZ_MSIX_PBA_TABLE_OFST 0x00008000
+/* sienaa0=pci_f0_bar4 */
+/* FR_BZ_MSIX_PBA_TABLE_STEP 4 */
+#define FR_CZ_MSIX_PBA_TABLE_ROWS 32
+
+#define FRF_BZ_MSIX_PBA_PEND_DWORD_LBN 0
+#define FRF_BZ_MSIX_PBA_PEND_DWORD_WIDTH 32
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_SRM_DBG_REG(64bit):
+ * SRAM debug access
+ */
+#define FR_AZ_SRM_DBG_REG_OFST 0x03000000
+/* sienaa0=net_func_bar2,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+#define FR_AZ_SRM_DBG_REG_STEP 8
+#define FR_CZ_SRM_DBG_REG_ROWS 262144
+#define FR_AB_SRM_DBG_REG_ROWS 2097152
+
+#define FRF_AZ_SRM_DBG_LBN 0
+#define FRF_AZ_SRM_DBG_WIDTH 64
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_CZ_TB_MSIX_PBA_TABLE(1bit):
+ * MSIX Pending Bit Array
+ */
+#define FR_CZ_TB_MSIX_PBA_TABLE_OFST 0x00008000
+/* sienaa0=pci_f0_bar4 */
+#define FR_CZ_TB_MSIX_PBA_TABLE_STEP 4
+#define FR_CZ_TB_MSIX_PBA_TABLE_ROWS 1024
+
+#define FRF_CZ_TB_MSIX_PBA_PEND_DWORD_LBN 0
+#define FRF_CZ_TB_MSIX_PBA_PEND_DWORD_WIDTH 32
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AA_INT_ACK_CHAR(32bit):
+ * CHAR interrupt acknowledge register
+ */
+#define FR_AA_INT_ACK_CHAR_OFST 0x00000060
+/* falcona0=char_func_bar0 */
+
+#define FRF_AA_INT_ACK_CHAR_FIELD_LBN 0
+#define FRF_AA_INT_ACK_CHAR_FIELD_WIDTH 32
+
+
+/*------------------------------------------------------------*/
+/* FS_DRIVER_EV */
+#define FSF_AZ_DRIVER_EV_SUBCODE_LBN 56
+#define FSF_AZ_DRIVER_EV_SUBCODE_WIDTH 4
+#define FSE_BZ_TX_DSC_ERROR_EV 15
+#define FSE_BZ_RX_DSC_ERROR_EV 14
+#define FSE_AA_RX_RECOVER_EV 11
+#define FSE_AZ_TIMER_EV 10
+#define FSE_AZ_TX_PKT_NON_TCP_UDP 9
+#define FSE_AZ_WAKE_UP_EV 6
+#define FSE_AZ_SRM_UPD_DONE_EV 5
+#define FSE_AB_EVQ_NOT_EN_EV 3
+#define FSE_AZ_EVQ_INIT_DONE_EV 2
+#define FSE_AZ_RX_DESCQ_FLS_DONE_EV 1
+#define FSE_AZ_TX_DESCQ_FLS_DONE_EV 0
+#define FSF_AZ_DRIVER_EV_SUBDATA_LBN 0
+#define FSF_AZ_DRIVER_EV_SUBDATA_WIDTH 14
+
+
+/*------------------------------------------------------------*/
+/* FS_EVENT_ENTRY */
+#define FSF_AZ_EV_CODE_LBN 60
+#define FSF_AZ_EV_CODE_WIDTH 4
+#define FSE_CZ_EV_CODE_MCDI_EV 12
+#define FSE_CZ_EV_CODE_USER_EV 8
+#define FSE_AZ_EV_CODE_DRV_GEN_EV 7
+#define FSE_AZ_EV_CODE_GLOBAL_EV 6
+#define FSE_AZ_EV_CODE_DRIVER_EV 5
+#define FSE_AZ_EV_CODE_TX_EV 2
+#define FSE_AZ_EV_CODE_RX_EV 0
+#define FSF_AZ_EV_DATA_LBN 0
+#define FSF_AZ_EV_DATA_WIDTH 60
+
+
+/*------------------------------------------------------------*/
+/* FS_GLOBAL_EV */
+#define FSF_BB_GLB_EV_RX_RECOVERY_LBN 12
+#define FSF_BB_GLB_EV_RX_RECOVERY_WIDTH 1
+#define FSF_AA_GLB_EV_RX_RECOVERY_LBN 11
+#define FSF_AA_GLB_EV_RX_RECOVERY_WIDTH 1
+#define FSF_BB_GLB_EV_XG_MGT_INTR_LBN 11
+#define FSF_BB_GLB_EV_XG_MGT_INTR_WIDTH 1
+#define FSF_AB_GLB_EV_XFP_PHY0_INTR_LBN 10
+#define FSF_AB_GLB_EV_XFP_PHY0_INTR_WIDTH 1
+#define FSF_AB_GLB_EV_XG_PHY0_INTR_LBN 9
+#define FSF_AB_GLB_EV_XG_PHY0_INTR_WIDTH 1
+#define FSF_AB_GLB_EV_G_PHY0_INTR_LBN 7
+#define FSF_AB_GLB_EV_G_PHY0_INTR_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/* FS_LEGACY_INT_VEC */
+#define FSF_AZ_NET_IVEC_FATAL_INT_LBN 64
+#define FSF_AZ_NET_IVEC_FATAL_INT_WIDTH 1
+#define FSF_AZ_NET_IVEC_INT_Q_LBN 40
+#define FSF_AZ_NET_IVEC_INT_Q_WIDTH 4
+#define FSF_AZ_NET_IVEC_INT_FLAG_LBN 32
+#define FSF_AZ_NET_IVEC_INT_FLAG_WIDTH 1
+#define FSF_AZ_NET_IVEC_EVQ_FIFO_HF_LBN 1
+#define FSF_AZ_NET_IVEC_EVQ_FIFO_HF_WIDTH 1
+#define FSF_AZ_NET_IVEC_EVQ_FIFO_AF_LBN 0
+#define FSF_AZ_NET_IVEC_EVQ_FIFO_AF_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/* FS_MC_XGMAC_FLTR_RULE_DEF */
+#define FSF_CZ_MC_XFRC_MODE_LBN 416
+#define FSF_CZ_MC_XFRC_MODE_WIDTH 1
+#define FSE_CZ_MC_XFRC_MODE_LAYERED 1
+#define FSE_CZ_MC_XFRC_MODE_SIMPLE 0
+#define FSF_CZ_MC_XFRC_HASH_LBN 384
+#define FSF_CZ_MC_XFRC_HASH_WIDTH 32
+#define FSF_CZ_MC_XFRC_LAYER4_BYTE_MASK_LBN 256
+#define FSF_CZ_MC_XFRC_LAYER4_BYTE_MASK_WIDTH 128
+#define FSF_CZ_MC_XFRC_LAYER3_BYTE_MASK_LBN 128
+#define FSF_CZ_MC_XFRC_LAYER3_BYTE_MASK_WIDTH 128
+#define FSF_CZ_MC_XFRC_LAYER2_OR_SIMPLE_BYTE_MASK_LBN 0
+#define FSF_CZ_MC_XFRC_LAYER2_OR_SIMPLE_BYTE_MASK_WIDTH 128
+
+
+/*------------------------------------------------------------*/
+/* FS_RX_EV */
+#define FSF_CZ_RX_EV_PKT_NOT_PARSED_LBN 58
+#define FSF_CZ_RX_EV_PKT_NOT_PARSED_WIDTH 1
+#define FSF_CZ_RX_EV_IPV6_PKT_LBN 57
+#define FSF_CZ_RX_EV_IPV6_PKT_WIDTH 1
+#define FSF_AZ_RX_EV_PKT_OK_LBN 56
+#define FSF_AZ_RX_EV_PKT_OK_WIDTH 1
+#define FSF_AZ_RX_EV_PAUSE_FRM_ERR_LBN 55
+#define FSF_AZ_RX_EV_PAUSE_FRM_ERR_WIDTH 1
+#define FSF_AZ_RX_EV_BUF_OWNER_ID_ERR_LBN 54
+#define FSF_AZ_RX_EV_BUF_OWNER_ID_ERR_WIDTH 1
+#define FSF_AZ_RX_EV_IP_FRAG_ERR_LBN 53
+#define FSF_AZ_RX_EV_IP_FRAG_ERR_WIDTH 1
+#define FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR_LBN 52
+#define FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR_WIDTH 1
+#define FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR_LBN 51
+#define FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR_WIDTH 1
+#define FSF_AZ_RX_EV_ETH_CRC_ERR_LBN 50
+#define FSF_AZ_RX_EV_ETH_CRC_ERR_WIDTH 1
+#define FSF_AZ_RX_EV_FRM_TRUNC_LBN 49
+#define FSF_AZ_RX_EV_FRM_TRUNC_WIDTH 1
+#define FSF_AA_RX_EV_DRIB_NIB_LBN 49
+#define FSF_AA_RX_EV_DRIB_NIB_WIDTH 1
+#define FSF_AZ_RX_EV_TOBE_DISC_LBN 47
+#define FSF_AZ_RX_EV_TOBE_DISC_WIDTH 1
+#define FSF_AZ_RX_EV_PKT_TYPE_LBN 44
+#define FSF_AZ_RX_EV_PKT_TYPE_WIDTH 3
+#define FSE_AZ_RX_EV_PKT_TYPE_VLAN_JUMBO 5
+#define FSE_AZ_RX_EV_PKT_TYPE_VLAN_LLC 4
+#define FSE_AZ_RX_EV_PKT_TYPE_VLAN 3
+#define FSE_AZ_RX_EV_PKT_TYPE_JUMBO 2
+#define FSE_AZ_RX_EV_PKT_TYPE_LLC 1
+#define FSE_AZ_RX_EV_PKT_TYPE_ETH 0
+#define FSF_AZ_RX_EV_HDR_TYPE_LBN 42
+#define FSF_AZ_RX_EV_HDR_TYPE_WIDTH 2
+#define FSE_AZ_RX_EV_HDR_TYPE_OTHER 3
+#define FSE_AB_RX_EV_HDR_TYPE_IPV4_OTHER 2
+#define FSE_CZ_RX_EV_HDR_TYPE_IPV4V6_OTHER 2
+#define FSE_AB_RX_EV_HDR_TYPE_IPV4_UDP 1
+#define FSE_CZ_RX_EV_HDR_TYPE_IPV4V6_UDP 1
+#define FSE_AB_RX_EV_HDR_TYPE_IPV4_TCP 0
+#define FSE_CZ_RX_EV_HDR_TYPE_IPV4V6_TCP 0
+#define FSF_AZ_RX_EV_DESC_Q_EMPTY_LBN 41
+#define FSF_AZ_RX_EV_DESC_Q_EMPTY_WIDTH 1
+#define FSF_AZ_RX_EV_MCAST_HASH_MATCH_LBN 40
+#define FSF_AZ_RX_EV_MCAST_HASH_MATCH_WIDTH 1
+#define FSF_AZ_RX_EV_MCAST_PKT_LBN 39
+#define FSF_AZ_RX_EV_MCAST_PKT_WIDTH 1
+#define FSF_AA_RX_EV_RECOVERY_FLAG_LBN 37
+#define FSF_AA_RX_EV_RECOVERY_FLAG_WIDTH 1
+#define FSF_AZ_RX_EV_Q_LABEL_LBN 32
+#define FSF_AZ_RX_EV_Q_LABEL_WIDTH 5
+#define FSF_AZ_RX_EV_JUMBO_CONT_LBN 31
+#define FSF_AZ_RX_EV_JUMBO_CONT_WIDTH 1
+#define FSF_AZ_RX_EV_PORT_LBN 30
+#define FSF_AZ_RX_EV_PORT_WIDTH 1
+#define FSF_AZ_RX_EV_BYTE_CNT_LBN 16
+#define FSF_AZ_RX_EV_BYTE_CNT_WIDTH 14
+#define FSF_AZ_RX_EV_SOP_LBN 15
+#define FSF_AZ_RX_EV_SOP_WIDTH 1
+#define FSF_AZ_RX_EV_ISCSI_PKT_OK_LBN 14
+#define FSF_AZ_RX_EV_ISCSI_PKT_OK_WIDTH 1
+#define FSF_AZ_RX_EV_ISCSI_DDIG_ERR_LBN 13
+#define FSF_AZ_RX_EV_ISCSI_DDIG_ERR_WIDTH 1
+#define FSF_AZ_RX_EV_ISCSI_HDIG_ERR_LBN 12
+#define FSF_AZ_RX_EV_ISCSI_HDIG_ERR_WIDTH 1
+#define FSF_AZ_RX_EV_DESC_PTR_LBN 0
+#define FSF_AZ_RX_EV_DESC_PTR_WIDTH 12
+
+
+/*------------------------------------------------------------*/
+/* FS_RX_KER_DESC */
+#define FSF_AZ_RX_KER_BUF_SIZE_LBN 48
+#define FSF_AZ_RX_KER_BUF_SIZE_WIDTH 14
+#define FSF_AZ_RX_KER_BUF_REGION_LBN 46
+#define FSF_AZ_RX_KER_BUF_REGION_WIDTH 2
+#define FSF_AZ_RX_KER_BUF_ADDR_LBN 0
+#define FSF_AZ_RX_KER_BUF_ADDR_WIDTH 46
+
+
+/*------------------------------------------------------------*/
+/* FS_RX_USER_DESC */
+#define FSF_AZ_RX_USER_2BYTE_OFFSET_LBN 20
+#define FSF_AZ_RX_USER_2BYTE_OFFSET_WIDTH 12
+#define FSF_AZ_RX_USER_BUF_ID_LBN 0
+#define FSF_AZ_RX_USER_BUF_ID_WIDTH 20
+
+
+/*------------------------------------------------------------*/
+/* FS_TX_EV */
+#define FSF_AZ_TX_EV_PKT_ERR_LBN 38
+#define FSF_AZ_TX_EV_PKT_ERR_WIDTH 1
+#define FSF_AZ_TX_EV_PKT_TOO_BIG_LBN 37
+#define FSF_AZ_TX_EV_PKT_TOO_BIG_WIDTH 1
+#define FSF_AZ_TX_EV_Q_LABEL_LBN 32
+#define FSF_AZ_TX_EV_Q_LABEL_WIDTH 5
+#define FSF_AZ_TX_EV_PORT_LBN 16
+#define FSF_AZ_TX_EV_PORT_WIDTH 1
+#define FSF_AZ_TX_EV_WQ_FF_FULL_LBN 15
+#define FSF_AZ_TX_EV_WQ_FF_FULL_WIDTH 1
+#define FSF_AZ_TX_EV_BUF_OWNER_ID_ERR_LBN 14
+#define FSF_AZ_TX_EV_BUF_OWNER_ID_ERR_WIDTH 1
+#define FSF_AZ_TX_EV_COMP_LBN 12
+#define FSF_AZ_TX_EV_COMP_WIDTH 1
+#define FSF_AZ_TX_EV_DESC_PTR_LBN 0
+#define FSF_AZ_TX_EV_DESC_PTR_WIDTH 12
+
+
+/*------------------------------------------------------------*/
+/* FS_TX_KER_DESC */
+#define FSF_AZ_TX_KER_CONT_LBN 62
+#define FSF_AZ_TX_KER_CONT_WIDTH 1
+#define FSF_AZ_TX_KER_BYTE_COUNT_LBN 48
+#define FSF_AZ_TX_KER_BYTE_COUNT_WIDTH 14
+#define FSF_AZ_TX_KER_BUF_REGION_LBN 46
+#define FSF_AZ_TX_KER_BUF_REGION_WIDTH 2
+#define FSF_AZ_TX_KER_BUF_ADDR_LBN 0
+#define FSF_AZ_TX_KER_BUF_ADDR_WIDTH 46
+
+
+/*------------------------------------------------------------*/
+/* FS_TX_USER_DESC */
+#define FSF_AZ_TX_USER_SW_EV_EN_LBN 48
+#define FSF_AZ_TX_USER_SW_EV_EN_WIDTH 1
+#define FSF_AZ_TX_USER_CONT_LBN 46
+#define FSF_AZ_TX_USER_CONT_WIDTH 1
+#define FSF_AZ_TX_USER_BYTE_CNT_LBN 33
+#define FSF_AZ_TX_USER_BYTE_CNT_WIDTH 13
+#define FSF_AZ_TX_USER_BUF_ID_LBN 13
+#define FSF_AZ_TX_USER_BUF_ID_WIDTH 20
+#define FSF_AZ_TX_USER_BYTE_OFS_LBN 0
+#define FSF_AZ_TX_USER_BYTE_OFS_WIDTH 13
+
+
+/*------------------------------------------------------------*/
+/* FS_USER_EV */
+#define FSF_CZ_USER_QID_LBN 32
+#define FSF_CZ_USER_QID_WIDTH 10
+#define FSF_CZ_USER_EV_REG_VALUE_LBN 0
+#define FSF_CZ_USER_EV_REG_VALUE_WIDTH 32
+
+
+#endif /* HOST_PROGMODEL_DEFS_H */
diff -r 0b5ca7cdbdfc -r b8c2a9aacba6
drivers/net/sfc/sfc_resource/ci/driver/efab/hardware/host_common_mac.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/net/sfc/sfc_resource/ci/driver/efab/hardware/host_common_mac.h
Fri Jan 08 13:06:22 2010 +0000
@@ -0,0 +1,730 @@
+/****************************************************************************
+ * Driver for Solarflare network controllers -
+ * resource management for Xen backend, OpenOnload, etc
+ * (including support for SFE4001 10GBT NIC)
+ *
+ * This file provides EtherFabric NIC hardware interface common
+ * definitions.
+ *
+ * Copyright 2005-2010: Solarflare Communications Inc,
+ * 9501 Jeronimo Road, Suite 250,
+ * Irvine, CA 92618, USA
+ *
+ * Developed and maintained by Solarflare Communications:
+ * <linux-xen-drivers@xxxxxxxxxxxxxx>
+ * <onload-dev@xxxxxxxxxxxxxx>
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation, incorporated herein by reference.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ ****************************************************************************
+ */
+
+#ifndef HOST_MAC_PROGMODEL_DEFS_H
+#define HOST_MAC_PROGMODEL_DEFS_H
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_MD_TXD_REG(128bit):
+ * PHY management transmit data register
+ */
+#define FR_AB_MD_TXD_REG_OFST 0x00000c00
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_MD_TXD_LBN 0
+#define FRF_AB_MD_TXD_WIDTH 16
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_MD_RXD_REG(128bit):
+ * PHY management receive data register
+ */
+#define FR_AB_MD_RXD_REG_OFST 0x00000c10
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_MD_RXD_LBN 0
+#define FRF_AB_MD_RXD_WIDTH 16
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_MD_CS_REG(128bit):
+ * PHY management configuration & status register
+ */
+#define FR_AB_MD_CS_REG_OFST 0x00000c20
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_MD_RD_EN_CMD_LBN 15
+#define FRF_AB_MD_RD_EN_CMD_WIDTH 1
+#define FRF_AB_MD_WR_EN_CMD_LBN 14
+#define FRF_AB_MD_WR_EN_CMD_WIDTH 1
+#define FRF_AB_MD_ADDR_CMD_LBN 13
+#define FRF_AB_MD_ADDR_CMD_WIDTH 1
+#define FRF_AB_MD_PT_LBN 7
+#define FRF_AB_MD_PT_WIDTH 3
+#define FRF_AB_MD_PL_LBN 6
+#define FRF_AB_MD_PL_WIDTH 1
+#define FRF_AB_MD_INT_CLR_LBN 5
+#define FRF_AB_MD_INT_CLR_WIDTH 1
+#define FRF_AB_MD_GC_LBN 4
+#define FRF_AB_MD_GC_WIDTH 1
+#define FRF_AB_MD_PRSP_LBN 3
+#define FRF_AB_MD_PRSP_WIDTH 1
+#define FRF_AB_MD_RIC_LBN 2
+#define FRF_AB_MD_RIC_WIDTH 1
+#define FRF_AB_MD_RDC_LBN 1
+#define FRF_AB_MD_RDC_WIDTH 1
+#define FRF_AB_MD_WRC_LBN 0
+#define FRF_AB_MD_WRC_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_MD_PHY_ADR_REG(128bit):
+ * PHY management PHY address register
+ */
+#define FR_AB_MD_PHY_ADR_REG_OFST 0x00000c30
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_MD_PHY_ADR_LBN 0
+#define FRF_AB_MD_PHY_ADR_WIDTH 16
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_MD_ID_REG(128bit):
+ * PHY management ID register
+ */
+#define FR_AB_MD_ID_REG_OFST 0x00000c40
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_MD_PRT_ADR_LBN 11
+#define FRF_AB_MD_PRT_ADR_WIDTH 5
+#define FRF_AB_MD_DEV_ADR_LBN 6
+#define FRF_AB_MD_DEV_ADR_WIDTH 5
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_MD_STAT_REG(128bit):
+ * PHY management status & mask register
+ */
+#define FR_AB_MD_STAT_REG_OFST 0x00000c50
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_MD_PINT_LBN 4
+#define FRF_AB_MD_PINT_WIDTH 1
+#define FRF_AB_MD_DONE_LBN 3
+#define FRF_AB_MD_DONE_WIDTH 1
+#define FRF_AB_MD_BSERR_LBN 2
+#define FRF_AB_MD_BSERR_WIDTH 1
+#define FRF_AB_MD_LNFL_LBN 1
+#define FRF_AB_MD_LNFL_WIDTH 1
+#define FRF_AB_MD_BSY_LBN 0
+#define FRF_AB_MD_BSY_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_MAC_STAT_DMA_REG(128bit):
+ * Port MAC statistical counter DMA register
+ */
+#define FR_AB_MAC_STAT_DMA_REG_OFST 0x00000c60
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_MAC_STAT_DMA_CMD_LBN 48
+#define FRF_AB_MAC_STAT_DMA_CMD_WIDTH 1
+#define FRF_AB_MAC_STAT_DMA_ADR_LBN 0
+#define FRF_AB_MAC_STAT_DMA_ADR_WIDTH 48
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_MAC_CTRL_REG(128bit):
+ * Port MAC control register
+ */
+#define FR_AB_MAC_CTRL_REG_OFST 0x00000c80
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_MAC_XOFF_VAL_LBN 16
+#define FRF_AB_MAC_XOFF_VAL_WIDTH 16
+#define FRF_BB_TXFIFO_DRAIN_EN_LBN 7
+#define FRF_BB_TXFIFO_DRAIN_EN_WIDTH 1
+#define FRF_AB_MAC_XG_DISTXCRC_LBN 5
+#define FRF_AB_MAC_XG_DISTXCRC_WIDTH 1
+#define FRF_AB_MAC_BCAD_ACPT_LBN 4
+#define FRF_AB_MAC_BCAD_ACPT_WIDTH 1
+#define FRF_AB_MAC_UC_PROM_LBN 3
+#define FRF_AB_MAC_UC_PROM_WIDTH 1
+#define FRF_AB_MAC_LINK_STATUS_LBN 2
+#define FRF_AB_MAC_LINK_STATUS_WIDTH 1
+#define FRF_AB_MAC_SPEED_LBN 0
+#define FRF_AB_MAC_SPEED_WIDTH 2
+#define FFE_AB_MAC_SPEED_10G 3
+#define FFE_AB_MAC_SPEED_1G 2
+#define FFE_AB_MAC_SPEED_100M 1
+#define FFE_AB_MAC_SPEED_10M 0
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_BB_GEN_MODE_REG(128bit):
+ * General Purpose mode register (external interrupt mask)
+ */
+#define FR_BB_GEN_MODE_REG_OFST 0x00000c90
+/* falconb0=net_func_bar2 */
+
+#define FRF_BB_XFP_PHY_INT_POL_SEL_LBN 3
+#define FRF_BB_XFP_PHY_INT_POL_SEL_WIDTH 1
+#define FRF_BB_XG_PHY_INT_POL_SEL_LBN 2
+#define FRF_BB_XG_PHY_INT_POL_SEL_WIDTH 1
+#define FRF_BB_XFP_PHY_INT_MASK_LBN 1
+#define FRF_BB_XFP_PHY_INT_MASK_WIDTH 1
+#define FRF_BB_XG_PHY_INT_MASK_LBN 0
+#define FRF_BB_XG_PHY_INT_MASK_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_MAC_MC_HASH_REG0(128bit):
+ * Multicast address hash table
+ */
+#define FR_AB_MAC_MC_HASH_REG0_OFST 0x00000ca0
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_MAC_MCAST_HASH0_LBN 0
+#define FRF_AB_MAC_MCAST_HASH0_WIDTH 128
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_MAC_MC_HASH_REG1(128bit):
+ * Multicast address hash table
+ */
+#define FR_AB_MAC_MC_HASH_REG1_OFST 0x00000cb0
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_MAC_MCAST_HASH1_LBN 0
+#define FRF_AB_MAC_MCAST_HASH1_WIDTH 128
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_GM_CFG1_REG(32bit):
+ * GMAC configuration register 1
+ */
+#define FR_AB_GM_CFG1_REG_OFST 0x00000e00
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_GM_SW_RST_LBN 31
+#define FRF_AB_GM_SW_RST_WIDTH 1
+#define FRF_AB_GM_SIM_RST_LBN 30
+#define FRF_AB_GM_SIM_RST_WIDTH 1
+#define FRF_AB_GM_RST_RX_MAC_CTL_LBN 19
+#define FRF_AB_GM_RST_RX_MAC_CTL_WIDTH 1
+#define FRF_AB_GM_RST_TX_MAC_CTL_LBN 18
+#define FRF_AB_GM_RST_TX_MAC_CTL_WIDTH 1
+#define FRF_AB_GM_RST_RX_FUNC_LBN 17
+#define FRF_AB_GM_RST_RX_FUNC_WIDTH 1
+#define FRF_AB_GM_RST_TX_FUNC_LBN 16
+#define FRF_AB_GM_RST_TX_FUNC_WIDTH 1
+#define FRF_AB_GM_LOOP_LBN 8
+#define FRF_AB_GM_LOOP_WIDTH 1
+#define FRF_AB_GM_RX_FC_EN_LBN 5
+#define FRF_AB_GM_RX_FC_EN_WIDTH 1
+#define FRF_AB_GM_TX_FC_EN_LBN 4
+#define FRF_AB_GM_TX_FC_EN_WIDTH 1
+#define FRF_AB_GM_SYNC_RXEN_LBN 3
+#define FRF_AB_GM_SYNC_RXEN_WIDTH 1
+#define FRF_AB_GM_RX_EN_LBN 2
+#define FRF_AB_GM_RX_EN_WIDTH 1
+#define FRF_AB_GM_SYNC_TXEN_LBN 1
+#define FRF_AB_GM_SYNC_TXEN_WIDTH 1
+#define FRF_AB_GM_TX_EN_LBN 0
+#define FRF_AB_GM_TX_EN_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_GM_CFG2_REG(32bit):
+ * GMAC configuration register 2
+ */
+#define FR_AB_GM_CFG2_REG_OFST 0x00000e10
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_GM_PAMBL_LEN_LBN 12
+#define FRF_AB_GM_PAMBL_LEN_WIDTH 4
+#define FRF_AB_GM_IF_MODE_LBN 8
+#define FRF_AB_GM_IF_MODE_WIDTH 2
+#define FFE_AB_IF_MODE_BYTE_MODE 2
+#define FFE_AB_IF_MODE_NIBBLE_MODE 1
+#define FRF_AB_GM_HUGE_FRM_EN_LBN 5
+#define FRF_AB_GM_HUGE_FRM_EN_WIDTH 1
+#define FRF_AB_GM_LEN_CHK_LBN 4
+#define FRF_AB_GM_LEN_CHK_WIDTH 1
+#define FRF_AB_GM_PAD_CRC_EN_LBN 2
+#define FRF_AB_GM_PAD_CRC_EN_WIDTH 1
+#define FRF_AB_GM_CRC_EN_LBN 1
+#define FRF_AB_GM_CRC_EN_WIDTH 1
+#define FRF_AB_GM_FD_LBN 0
+#define FRF_AB_GM_FD_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_GM_IPG_REG(32bit):
+ * GMAC IPG register
+ */
+#define FR_AB_GM_IPG_REG_OFST 0x00000e20
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_GM_NONB2B_IPG1_LBN 24
+#define FRF_AB_GM_NONB2B_IPG1_WIDTH 7
+#define FRF_AB_GM_NONB2B_IPG2_LBN 16
+#define FRF_AB_GM_NONB2B_IPG2_WIDTH 7
+#define FRF_AB_GM_MIN_IPG_ENF_LBN 8
+#define FRF_AB_GM_MIN_IPG_ENF_WIDTH 8
+#define FRF_AB_GM_B2B_IPG_LBN 0
+#define FRF_AB_GM_B2B_IPG_WIDTH 7
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_GM_HD_REG(32bit):
+ * GMAC half duplex register
+ */
+#define FR_AB_GM_HD_REG_OFST 0x00000e30
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_GM_ALT_BOFF_VAL_LBN 20
+#define FRF_AB_GM_ALT_BOFF_VAL_WIDTH 4
+#define FRF_AB_GM_ALT_BOFF_EN_LBN 19
+#define FRF_AB_GM_ALT_BOFF_EN_WIDTH 1
+#define FRF_AB_GM_BP_NO_BOFF_LBN 18
+#define FRF_AB_GM_BP_NO_BOFF_WIDTH 1
+#define FRF_AB_GM_DIS_BOFF_LBN 17
+#define FRF_AB_GM_DIS_BOFF_WIDTH 1
+#define FRF_AB_GM_EXDEF_TX_EN_LBN 16
+#define FRF_AB_GM_EXDEF_TX_EN_WIDTH 1
+#define FRF_AB_GM_RTRY_LIMIT_LBN 12
+#define FRF_AB_GM_RTRY_LIMIT_WIDTH 4
+#define FRF_AB_GM_COL_WIN_LBN 0
+#define FRF_AB_GM_COL_WIN_WIDTH 10
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_GM_MAX_FLEN_REG(32bit):
+ * GMAC maximum frame length register
+ */
+#define FR_AB_GM_MAX_FLEN_REG_OFST 0x00000e40
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_GM_MAX_FLEN_LBN 0
+#define FRF_AB_GM_MAX_FLEN_WIDTH 16
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_GM_TEST_REG(32bit):
+ * GMAC test register
+ */
+#define FR_AB_GM_TEST_REG_OFST 0x00000e70
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_GM_MAX_BOFF_LBN 3
+#define FRF_AB_GM_MAX_BOFF_WIDTH 1
+#define FRF_AB_GM_REG_TX_FLOW_EN_LBN 2
+#define FRF_AB_GM_REG_TX_FLOW_EN_WIDTH 1
+#define FRF_AB_GM_TEST_PAUSE_LBN 1
+#define FRF_AB_GM_TEST_PAUSE_WIDTH 1
+#define FRF_AB_GM_SHORT_SLOT_LBN 0
+#define FRF_AB_GM_SHORT_SLOT_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_GM_ADR1_REG(32bit):
+ * GMAC station address register 1
+ */
+#define FR_AB_GM_ADR1_REG_OFST 0x00000f00
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_GM_ADR_B0_LBN 24
+#define FRF_AB_GM_ADR_B0_WIDTH 8
+#define FRF_AB_GM_ADR_B1_LBN 16
+#define FRF_AB_GM_ADR_B1_WIDTH 8
+#define FRF_AB_GM_ADR_B2_LBN 8
+#define FRF_AB_GM_ADR_B2_WIDTH 8
+#define FRF_AB_GM_ADR_B3_LBN 0
+#define FRF_AB_GM_ADR_B3_WIDTH 8
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_GM_ADR2_REG(32bit):
+ * GMAC station address register 2
+ */
+#define FR_AB_GM_ADR2_REG_OFST 0x00000f10
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_GM_ADR_B4_LBN 24
+#define FRF_AB_GM_ADR_B4_WIDTH 8
+#define FRF_AB_GM_ADR_B5_LBN 16
+#define FRF_AB_GM_ADR_B5_WIDTH 8
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_GMF_CFG0_REG(32bit):
+ * GMAC FIFO configuration register 0
+ */
+#define FR_AB_GMF_CFG0_REG_OFST 0x00000f20
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_GMF_FTFENRPLY_LBN 20
+#define FRF_AB_GMF_FTFENRPLY_WIDTH 1
+#define FRF_AB_GMF_STFENRPLY_LBN 19
+#define FRF_AB_GMF_STFENRPLY_WIDTH 1
+#define FRF_AB_GMF_FRFENRPLY_LBN 18
+#define FRF_AB_GMF_FRFENRPLY_WIDTH 1
+#define FRF_AB_GMF_SRFENRPLY_LBN 17
+#define FRF_AB_GMF_SRFENRPLY_WIDTH 1
+#define FRF_AB_GMF_WTMENRPLY_LBN 16
+#define FRF_AB_GMF_WTMENRPLY_WIDTH 1
+#define FRF_AB_GMF_FTFENREQ_LBN 12
+#define FRF_AB_GMF_FTFENREQ_WIDTH 1
+#define FRF_AB_GMF_STFENREQ_LBN 11
+#define FRF_AB_GMF_STFENREQ_WIDTH 1
+#define FRF_AB_GMF_FRFENREQ_LBN 10
+#define FRF_AB_GMF_FRFENREQ_WIDTH 1
+#define FRF_AB_GMF_SRFENREQ_LBN 9
+#define FRF_AB_GMF_SRFENREQ_WIDTH 1
+#define FRF_AB_GMF_WTMENREQ_LBN 8
+#define FRF_AB_GMF_WTMENREQ_WIDTH 1
+#define FRF_AB_GMF_HSTRSTFT_LBN 4
+#define FRF_AB_GMF_HSTRSTFT_WIDTH 1
+#define FRF_AB_GMF_HSTRSTST_LBN 3
+#define FRF_AB_GMF_HSTRSTST_WIDTH 1
+#define FRF_AB_GMF_HSTRSTFR_LBN 2
+#define FRF_AB_GMF_HSTRSTFR_WIDTH 1
+#define FRF_AB_GMF_HSTRSTSR_LBN 1
+#define FRF_AB_GMF_HSTRSTSR_WIDTH 1
+#define FRF_AB_GMF_HSTRSTWT_LBN 0
+#define FRF_AB_GMF_HSTRSTWT_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_GMF_CFG1_REG(32bit):
+ * GMAC FIFO configuration register 1
+ */
+#define FR_AB_GMF_CFG1_REG_OFST 0x00000f30
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_GMF_CFGFRTH_LBN 16
+#define FRF_AB_GMF_CFGFRTH_WIDTH 5
+#define FRF_AB_GMF_CFGXOFFRTX_LBN 0
+#define FRF_AB_GMF_CFGXOFFRTX_WIDTH 16
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_GMF_CFG2_REG(32bit):
+ * GMAC FIFO configuration register 2
+ */
+#define FR_AB_GMF_CFG2_REG_OFST 0x00000f40
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_GMF_CFGHWM_LBN 16
+#define FRF_AB_GMF_CFGHWM_WIDTH 6
+#define FRF_AB_GMF_CFGLWM_LBN 0
+#define FRF_AB_GMF_CFGLWM_WIDTH 6
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_GMF_CFG3_REG(32bit):
+ * GMAC FIFO configuration register 3
+ */
+#define FR_AB_GMF_CFG3_REG_OFST 0x00000f50
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_GMF_CFGHWMFT_LBN 16
+#define FRF_AB_GMF_CFGHWMFT_WIDTH 6
+#define FRF_AB_GMF_CFGFTTH_LBN 0
+#define FRF_AB_GMF_CFGFTTH_WIDTH 6
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_GMF_CFG4_REG(32bit):
+ * GMAC FIFO configuration register 4
+ */
+#define FR_AB_GMF_CFG4_REG_OFST 0x00000f60
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_GMF_HSTFLTRFRM_LBN 0
+#define FRF_AB_GMF_HSTFLTRFRM_WIDTH 18
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_GMF_CFG5_REG(32bit):
+ * GMAC FIFO configuration register 5
+ */
+#define FR_AB_GMF_CFG5_REG_OFST 0x00000f70
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_GMF_CFGHDPLX_LBN 22
+#define FRF_AB_GMF_CFGHDPLX_WIDTH 1
+#define FRF_AB_GMF_SRFULL_LBN 21
+#define FRF_AB_GMF_SRFULL_WIDTH 1
+#define FRF_AB_GMF_HSTSRFULLCLR_LBN 20
+#define FRF_AB_GMF_HSTSRFULLCLR_WIDTH 1
+#define FRF_AB_GMF_CFGBYTMODE_LBN 19
+#define FRF_AB_GMF_CFGBYTMODE_WIDTH 1
+#define FRF_AB_GMF_HSTDRPLT64_LBN 18
+#define FRF_AB_GMF_HSTDRPLT64_WIDTH 1
+#define FRF_AB_GMF_HSTFLTRFRMDC_LBN 0
+#define FRF_AB_GMF_HSTFLTRFRMDC_WIDTH 18
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_XM_ADR_LO_REG(128bit):
+ * XGMAC address register low
+ */
+#define FR_AB_XM_ADR_LO_REG_OFST 0x00001200
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_XM_ADR_LO_LBN 0
+#define FRF_AB_XM_ADR_LO_WIDTH 32
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_XM_ADR_HI_REG(128bit):
+ * XGMAC address register high
+ */
+#define FR_AB_XM_ADR_HI_REG_OFST 0x00001210
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_XM_ADR_HI_LBN 0
+#define FRF_AB_XM_ADR_HI_WIDTH 16
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_XM_GLB_CFG_REG(128bit):
+ * XGMAC global configuration
+ */
+#define FR_AB_XM_GLB_CFG_REG_OFST 0x00001220
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_XM_RMTFLT_GEN_LBN 17
+#define FRF_AB_XM_RMTFLT_GEN_WIDTH 1
+#define FRF_AB_XM_DEBUG_MODE_LBN 16
+#define FRF_AB_XM_DEBUG_MODE_WIDTH 1
+#define FRF_AB_XM_RX_STAT_EN_LBN 11
+#define FRF_AB_XM_RX_STAT_EN_WIDTH 1
+#define FRF_AB_XM_TX_STAT_EN_LBN 10
+#define FRF_AB_XM_TX_STAT_EN_WIDTH 1
+#define FRF_AB_XM_RX_JUMBO_MODE_LBN 6
+#define FRF_AB_XM_RX_JUMBO_MODE_WIDTH 1
+#define FRF_AB_XM_WAN_MODE_LBN 5
+#define FRF_AB_XM_WAN_MODE_WIDTH 1
+#define FRF_AB_XM_INTCLR_MODE_LBN 3
+#define FRF_AB_XM_INTCLR_MODE_WIDTH 1
+#define FRF_AB_XM_CORE_RST_LBN 0
+#define FRF_AB_XM_CORE_RST_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_XM_TX_CFG_REG(128bit):
+ * XGMAC transmit configuration
+ */
+#define FR_AB_XM_TX_CFG_REG_OFST 0x00001230
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_XM_TX_PROG_LBN 24
+#define FRF_AB_XM_TX_PROG_WIDTH 1
+#define FRF_AB_XM_IPG_LBN 16
+#define FRF_AB_XM_IPG_WIDTH 4
+#define FRF_AB_XM_FCNTL_LBN 10
+#define FRF_AB_XM_FCNTL_WIDTH 1
+#define FRF_AB_XM_TXCRC_LBN 8
+#define FRF_AB_XM_TXCRC_WIDTH 1
+#define FRF_AB_XM_EDRC_LBN 6
+#define FRF_AB_XM_EDRC_WIDTH 1
+#define FRF_AB_XM_AUTO_PAD_LBN 5
+#define FRF_AB_XM_AUTO_PAD_WIDTH 1
+#define FRF_AB_XM_TX_PRMBL_LBN 2
+#define FRF_AB_XM_TX_PRMBL_WIDTH 1
+#define FRF_AB_XM_TXEN_LBN 1
+#define FRF_AB_XM_TXEN_WIDTH 1
+#define FRF_AB_XM_TX_RST_LBN 0
+#define FRF_AB_XM_TX_RST_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_XM_RX_CFG_REG(128bit):
+ * XGMAC receive configuration
+ */
+#define FR_AB_XM_RX_CFG_REG_OFST 0x00001240
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_XM_PASS_LENERR_LBN 26
+#define FRF_AB_XM_PASS_LENERR_WIDTH 1
+#define FRF_AB_XM_PASS_CRC_ERR_LBN 25
+#define FRF_AB_XM_PASS_CRC_ERR_WIDTH 1
+#define FRF_AB_XM_PASS_PRMBLE_ERR_LBN 24
+#define FRF_AB_XM_PASS_PRMBLE_ERR_WIDTH 1
+#define FRF_AB_XM_REJ_BCAST_LBN 20
+#define FRF_AB_XM_REJ_BCAST_WIDTH 1
+#define FRF_AB_XM_ACPT_ALL_MCAST_LBN 11
+#define FRF_AB_XM_ACPT_ALL_MCAST_WIDTH 1
+#define FRF_AB_XM_ACPT_ALL_UCAST_LBN 9
+#define FRF_AB_XM_ACPT_ALL_UCAST_WIDTH 1
+#define FRF_AB_XM_AUTO_DEPAD_LBN 8
+#define FRF_AB_XM_AUTO_DEPAD_WIDTH 1
+#define FRF_AB_XM_RXCRC_LBN 3
+#define FRF_AB_XM_RXCRC_WIDTH 1
+#define FRF_AB_XM_RX_PRMBL_LBN 2
+#define FRF_AB_XM_RX_PRMBL_WIDTH 1
+#define FRF_AB_XM_RXEN_LBN 1
+#define FRF_AB_XM_RXEN_WIDTH 1
+#define FRF_AB_XM_RX_RST_LBN 0
+#define FRF_AB_XM_RX_RST_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_XM_MGT_INT_MASK(128bit):
+ * documentation to be written for sum_XM_MGT_INT_MASK
+ */
+#define FR_AB_XM_MGT_INT_MASK_OFST 0x00001250
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_XM_MSK_STA_INTR_LBN 16
+#define FRF_AB_XM_MSK_STA_INTR_WIDTH 1
+#define FRF_AB_XM_MSK_STAT_CNTR_HF_LBN 9
+#define FRF_AB_XM_MSK_STAT_CNTR_HF_WIDTH 1
+#define FRF_AB_XM_MSK_STAT_CNTR_OF_LBN 8
+#define FRF_AB_XM_MSK_STAT_CNTR_OF_WIDTH 1
+#define FRF_AB_XM_MSK_PRMBLE_ERR_LBN 2
+#define FRF_AB_XM_MSK_PRMBLE_ERR_WIDTH 1
+#define FRF_AB_XM_MSK_RMTFLT_LBN 1
+#define FRF_AB_XM_MSK_RMTFLT_WIDTH 1
+#define FRF_AB_XM_MSK_LCLFLT_LBN 0
+#define FRF_AB_XM_MSK_LCLFLT_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_XM_FC_REG(128bit):
+ * XGMAC flow control register
+ */
+#define FR_AB_XM_FC_REG_OFST 0x00001270
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_XM_PAUSE_TIME_LBN 16
+#define FRF_AB_XM_PAUSE_TIME_WIDTH 16
+#define FRF_AB_XM_RX_MAC_STAT_LBN 11
+#define FRF_AB_XM_RX_MAC_STAT_WIDTH 1
+#define FRF_AB_XM_TX_MAC_STAT_LBN 10
+#define FRF_AB_XM_TX_MAC_STAT_WIDTH 1
+#define FRF_AB_XM_MCNTL_PASS_LBN 8
+#define FRF_AB_XM_MCNTL_PASS_WIDTH 2
+#define FRF_AB_XM_REJ_CNTL_UCAST_LBN 6
+#define FRF_AB_XM_REJ_CNTL_UCAST_WIDTH 1
+#define FRF_AB_XM_REJ_CNTL_MCAST_LBN 5
+#define FRF_AB_XM_REJ_CNTL_MCAST_WIDTH 1
+#define FRF_AB_XM_ZPAUSE_LBN 2
+#define FRF_AB_XM_ZPAUSE_WIDTH 1
+#define FRF_AB_XM_XMIT_PAUSE_LBN 1
+#define FRF_AB_XM_XMIT_PAUSE_WIDTH 1
+#define FRF_AB_XM_DIS_FCNTL_LBN 0
+#define FRF_AB_XM_DIS_FCNTL_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_XM_PAUSE_TIME_REG(128bit):
+ * XGMAC pause time register
+ */
+#define FR_AB_XM_PAUSE_TIME_REG_OFST 0x00001290
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_XM_TX_PAUSE_CNT_LBN 16
+#define FRF_AB_XM_TX_PAUSE_CNT_WIDTH 16
+#define FRF_AB_XM_RX_PAUSE_CNT_LBN 0
+#define FRF_AB_XM_RX_PAUSE_CNT_WIDTH 16
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_XM_TX_PARAM_REG(128bit):
+ * XGMAC transmit parameter register
+ */
+#define FR_AB_XM_TX_PARAM_REG_OFST 0x000012d0
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_XM_TX_JUMBO_MODE_LBN 31
+#define FRF_AB_XM_TX_JUMBO_MODE_WIDTH 1
+#define FRF_AB_XM_MAX_TX_FRM_SIZE_HI_LBN 19
+#define FRF_AB_XM_MAX_TX_FRM_SIZE_HI_WIDTH 11
+#define FRF_AB_XM_MAX_TX_FRM_SIZE_LO_LBN 16
+#define FRF_AB_XM_MAX_TX_FRM_SIZE_LO_WIDTH 3
+#define FRF_AB_XM_PAD_CHAR_LBN 0
+#define FRF_AB_XM_PAD_CHAR_WIDTH 8
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_XM_RX_PARAM_REG(128bit):
+ * XGMAC receive parameter register
+ */
+#define FR_AB_XM_RX_PARAM_REG_OFST 0x000012e0
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_XM_MAX_RX_FRM_SIZE_HI_LBN 3
+#define FRF_AB_XM_MAX_RX_FRM_SIZE_HI_WIDTH 11
+#define FRF_AB_XM_MAX_RX_FRM_SIZE_LO_LBN 0
+#define FRF_AB_XM_MAX_RX_FRM_SIZE_LO_WIDTH 3
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_XM_MGT_INT_MSK_REG(128bit):
+ * XGMAC management interrupt mask register
+ */
+#define FR_AB_XM_MGT_INT_MSK_REG_OFST 0x000012f0
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_XM_STAT_CNTR_OF_LBN 9
+#define FRF_AB_XM_STAT_CNTR_OF_WIDTH 1
+#define FRF_AB_XM_STAT_CNTR_HF_LBN 8
+#define FRF_AB_XM_STAT_CNTR_HF_WIDTH 1
+#define FRF_AB_XM_PRMBLE_ERR_LBN 2
+#define FRF_AB_XM_PRMBLE_ERR_WIDTH 1
+#define FRF_AB_XM_RMTFLT_LBN 1
+#define FRF_AB_XM_RMTFLT_WIDTH 1
+#define FRF_AB_XM_LCLFLT_LBN 0
+#define FRF_AB_XM_LCLFLT_WIDTH 1
+
+
+#endif /* HOST_MAC_PROGMODEL_DEFS_H */
diff -r 0b5ca7cdbdfc -r b8c2a9aacba6
drivers/net/sfc/sfc_resource/ci/driver/efab/hardware/host_common_pci_defs.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++
b/drivers/net/sfc/sfc_resource/ci/driver/efab/hardware/host_common_pci_defs.h
Fri Jan 08 13:06:22 2010 +0000
@@ -0,0 +1,2057 @@
+/****************************************************************************
+ * Driver for Solarflare network controllers -
+ * resource management for Xen backend, OpenOnload, etc
+ * (including support for SFE4001 10GBT NIC)
+ *
+ * This file provides EtherFabric NIC hardware interface common
+ * definitions.
+ *
+ * Copyright 2005-2010: Solarflare Communications Inc,
+ * 9501 Jeronimo Road, Suite 250,
+ * Irvine, CA 92618, USA
+ *
+ * Developed and maintained by Solarflare Communications:
+ * <linux-xen-drivers@xxxxxxxxxxxxxx>
+ * <onload-dev@xxxxxxxxxxxxxx>
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation, incorporated herein by reference.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ ****************************************************************************
+ */
+
+#ifndef PCI_PROGMODEL_DEFS_H
+#define PCI_PROGMODEL_DEFS_H
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_PM_CS_REG(16bit):
+ * Power management control & status register
+ */
+#define PCR_AZ_PM_CS_REG 0x00000044
+/* falcona0,falconb0=pci_f0_config,sienaa0=pci_f0_config */
+
+#define PCRF_AZ_PM_PME_STAT_LBN 15
+#define PCRF_AZ_PM_PME_STAT_WIDTH 1
+#define PCRF_AZ_PM_DAT_SCALE_LBN 13
+#define PCRF_AZ_PM_DAT_SCALE_WIDTH 2
+#define PCRF_AZ_PM_DAT_SEL_LBN 9
+#define PCRF_AZ_PM_DAT_SEL_WIDTH 4
+#define PCRF_AZ_PM_PME_EN_LBN 8
+#define PCRF_AZ_PM_PME_EN_WIDTH 1
+#define PCRF_CZ_NO_SOFT_RESET_LBN 3
+#define PCRF_CZ_NO_SOFT_RESET_WIDTH 1
+#define PCRF_AZ_PM_PWR_ST_LBN 0
+#define PCRF_AZ_PM_PWR_ST_WIDTH 2
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_VEND_ID_REG(16bit):
+ * Vendor ID register
+ */
+#define PCR_AZ_VEND_ID_REG 0x00000000
+/* sienaa0=pci_f0_config,falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AZ_VEND_ID_LBN 0
+#define PCRF_AZ_VEND_ID_WIDTH 16
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_DEV_ID_REG(16bit):
+ * Device ID register
+ */
+#define PCR_AZ_DEV_ID_REG 0x00000002
+/* sienaa0=pci_f0_config,falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AZ_DEV_ID_LBN 0
+#define PCRF_AZ_DEV_ID_WIDTH 16
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_REV_ID_REG(8bit):
+ * Class code & revision ID register
+ */
+#define PCR_AZ_REV_ID_REG 0x00000008
+/* sienaa0=pci_f0_config,falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AZ_REV_ID_LBN 0
+#define PCRF_AZ_REV_ID_WIDTH 8
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_CC_REG(24bit):
+ * Class code register
+ */
+#define PCR_AZ_CC_REG 0x00000009
+/* sienaa0=pci_f0_config,falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AZ_BASE_CC_LBN 16
+#define PCRF_AZ_BASE_CC_WIDTH 8
+#define PCRF_AZ_SUB_CC_LBN 8
+#define PCRF_AZ_SUB_CC_WIDTH 8
+#define PCRF_AZ_PROG_IF_LBN 0
+#define PCRF_AZ_PROG_IF_WIDTH 8
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_MST_LAT_REG(8bit):
+ * Master latency timer register
+ */
+#define PCR_AZ_MST_LAT_REG 0x0000000d
+/* sienaa0=pci_f0_config,falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AZ_MST_LAT_LBN 0
+#define PCRF_AZ_MST_LAT_WIDTH 8
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_HDR_TYPE_REG(8bit):
+ * Header type register
+ */
+#define PCR_AZ_HDR_TYPE_REG 0x0000000e
+/* sienaa0=pci_f0_config,falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AZ_MULT_FUNC_LBN 7
+#define PCRF_AZ_MULT_FUNC_WIDTH 1
+#define PCRF_AZ_TYPE_LBN 0
+#define PCRF_AZ_TYPE_WIDTH 7
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_BIST_REG(8bit):
+ * BIST register
+ */
+#define PCR_AZ_BIST_REG 0x0000000f
+/* sienaa0=pci_f0_config,falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AZ_BIST_LBN 0
+#define PCRF_AZ_BIST_WIDTH 8
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_BAR4_LO_REG(32bit):
+ * Primary function base address register 2 low bits
+ */
+#define PCR_CZ_BAR4_LO_REG 0x00000020
+/* sienaa0=pci_f0_config */
+
+#define PCRF_CZ_BAR4_LO_LBN 4
+#define PCRF_CZ_BAR4_LO_WIDTH 28
+#define PCRF_CZ_BAR4_PREF_LBN 3
+#define PCRF_CZ_BAR4_PREF_WIDTH 1
+#define PCRF_CZ_BAR4_TYPE_LBN 1
+#define PCRF_CZ_BAR4_TYPE_WIDTH 2
+#define PCRF_CZ_BAR4_IOM_LBN 0
+#define PCRF_CZ_BAR4_IOM_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_SS_ID_REG(16bit):
+ * Sub-system ID register
+ */
+#define PCR_AZ_SS_ID_REG 0x0000002e
+/* sienaa0=pci_f0_config,falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AZ_SS_ID_LBN 0
+#define PCRF_AZ_SS_ID_WIDTH 16
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_EXPROM_BAR_REG(32bit):
+ * Expansion ROM base address register
+ */
+#define PCR_AZ_EXPROM_BAR_REG 0x00000030
+/* sienaa0=pci_f0_config,falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AZ_EXPROM_BAR_LBN 11
+#define PCRF_AZ_EXPROM_BAR_WIDTH 21
+#define PCRF_AB_EXPROM_MIN_SIZE_LBN 2
+#define PCRF_AB_EXPROM_MIN_SIZE_WIDTH 9
+#define PCRF_CZ_EXPROM_MIN_SIZE_LBN 1
+#define PCRF_CZ_EXPROM_MIN_SIZE_WIDTH 10
+#define PCRF_AB_EXPROM_FEATURE_ENABLE_LBN 1
+#define PCRF_AB_EXPROM_FEATURE_ENABLE_WIDTH 1
+#define PCRF_AZ_EXPROM_EN_LBN 0
+#define PCRF_AZ_EXPROM_EN_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_CAP_PTR_REG(8bit):
+ * Capability pointer register
+ */
+#define PCR_AZ_CAP_PTR_REG 0x00000034
+/* sienaa0=pci_f0_config,falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AZ_CAP_PTR_LBN 0
+#define PCRF_AZ_CAP_PTR_WIDTH 8
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_INT_LINE_REG(8bit):
+ * Interrupt line register
+ */
+#define PCR_AZ_INT_LINE_REG 0x0000003c
+/* sienaa0=pci_f0_config,falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AZ_INT_LINE_LBN 0
+#define PCRF_AZ_INT_LINE_WIDTH 8
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_INT_PIN_REG(8bit):
+ * Interrupt pin register
+ */
+#define PCR_AZ_INT_PIN_REG 0x0000003d
+/* sienaa0=pci_f0_config,falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AZ_INT_PIN_LBN 0
+#define PCRF_AZ_INT_PIN_WIDTH 8
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_MSI_CAP_ID_REG(8bit):
+ * MSI capability ID
+ */
+#define PCR_AZ_MSI_CAP_ID_REG 0x00000050
+/* sienaa0=pci_f0_config,falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AZ_MSI_CAP_ID_LBN 0
+#define PCRF_AZ_MSI_CAP_ID_WIDTH 8
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_MSI_NXT_PTR_REG(8bit):
+ * MSI next item pointer
+ */
+#define PCR_AZ_MSI_NXT_PTR_REG 0x00000051
+/* sienaa0=pci_f0_config,falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AZ_MSI_NXT_PTR_LBN 0
+#define PCRF_AZ_MSI_NXT_PTR_WIDTH 8
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_MSI_CTL_REG(16bit):
+ * MSI control register
+ */
+#define PCR_AZ_MSI_CTL_REG 0x00000052
+/* sienaa0=pci_f0_config,falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AZ_MSI_64_EN_LBN 7
+#define PCRF_AZ_MSI_64_EN_WIDTH 1
+#define PCRF_AZ_MSI_MULT_MSG_EN_LBN 4
+#define PCRF_AZ_MSI_MULT_MSG_EN_WIDTH 3
+#define PCRF_AZ_MSI_MULT_MSG_CAP_LBN 1
+#define PCRF_AZ_MSI_MULT_MSG_CAP_WIDTH 3
+#define PCRF_AZ_MSI_EN_LBN 0
+#define PCRF_AZ_MSI_EN_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_MSI_ADR_HI_REG(32bit):
+ * MSI high 32 bits address register
+ */
+#define PCR_AZ_MSI_ADR_HI_REG 0x00000058
+/* sienaa0=pci_f0_config,falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AZ_MSI_ADR_HI_LBN 0
+#define PCRF_AZ_MSI_ADR_HI_WIDTH 32
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_PCIE_CAP_LIST_REG(16bit):
+ * PCIe capability list register
+ */
+#define PCR_CZ_PCIE_CAP_LIST_REG 0x00000070
+/* sienaa0=pci_f0_config */
+/*
+ * PCR_AB_PCIE_CAP_LIST_REG(16bit):
+ * PCIe capability list register
+ */
+#define PCR_AB_PCIE_CAP_LIST_REG 0x00000060
+/* falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AZ_PCIE_NXT_PTR_LBN 8
+#define PCRF_AZ_PCIE_NXT_PTR_WIDTH 8
+#define PCRF_AZ_PCIE_CAP_ID_LBN 0
+#define PCRF_AZ_PCIE_CAP_ID_WIDTH 8
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_DEV_CAP_REG(28bit):
+ * PCIe device capabilities register
+ */
+#define PCR_CZ_DEV_CAP_REG 0x00000074
+/* sienaa0=pci_f0_config */
+/*
+ * PCR_AB_DEV_CAP_REG(28bit):
+ * PCIe device capabilities register
+ */
+#define PCR_AB_DEV_CAP_REG 0x00000064
+/* falcona0,falconb0=pci_f0_config */
+
+#define PCRF_CZ_CAP_FN_LEVEL_RESET_LBN 28
+#define PCRF_CZ_CAP_FN_LEVEL_RESET_WIDTH 1
+#define PCRF_AZ_CAP_SLOT_PWR_SCL_LBN 26
+#define PCRF_AZ_CAP_SLOT_PWR_SCL_WIDTH 2
+#define PCRF_AZ_CAP_SLOT_PWR_VAL_LBN 18
+#define PCRF_AZ_CAP_SLOT_PWR_VAL_WIDTH 8
+#define PCRF_CZ_ROLE_BASE_ERR_REPORTING_LBN 15
+#define PCRF_CZ_ROLE_BASE_ERR_REPORTING_WIDTH 1
+#define PCRF_AB_PWR_IND_LBN 14
+#define PCRF_AB_PWR_IND_WIDTH 1
+#define PCRF_AB_ATTN_IND_LBN 13
+#define PCRF_AB_ATTN_IND_WIDTH 1
+#define PCRF_AB_ATTN_BUTTON_LBN 12
+#define PCRF_AB_ATTN_BUTTON_WIDTH 1
+#define PCRF_AZ_ENDPT_L1_LAT_LBN 9
+#define PCRF_AZ_ENDPT_L1_LAT_WIDTH 3
+#define PCRF_AZ_ENDPT_L0_LAT_LBN 6
+#define PCRF_AZ_ENDPT_L0_LAT_WIDTH 3
+#define PCRF_AZ_TAG_FIELD_LBN 5
+#define PCRF_AZ_TAG_FIELD_WIDTH 1
+#define PCRF_AZ_PHAN_FUNC_LBN 3
+#define PCRF_AZ_PHAN_FUNC_WIDTH 2
+#define PCRF_AZ_MAX_PAYL_SIZE_SUPT_LBN 0
+#define PCRF_AZ_MAX_PAYL_SIZE_SUPT_WIDTH 3
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_DEV_CTL_REG(16bit):
+ * PCIe device control register
+ */
+#define PCR_CZ_DEV_CTL_REG 0x00000078
+/* sienaa0=pci_f0_config */
+/*
+ * PCR_AB_DEV_CTL_REG(16bit):
+ * PCIe device control register
+ */
+#define PCR_AB_DEV_CTL_REG 0x00000068
+/* falcona0,falconb0=pci_f0_config */
+
+#define PCRF_CZ_FN_LEVEL_RESET_LBN 15
+#define PCRF_CZ_FN_LEVEL_RESET_WIDTH 1
+#define PCRF_AZ_MAX_RD_REQ_SIZE_LBN 12
+#define PCRF_AZ_MAX_RD_REQ_SIZE_WIDTH 3
+#define PCFE_AZ_MAX_RD_REQ_SIZE_4096 5
+#define PCFE_AZ_MAX_RD_REQ_SIZE_2048 4
+#define PCFE_AZ_MAX_RD_REQ_SIZE_1024 3
+#define PCFE_AZ_MAX_RD_REQ_SIZE_512 2
+#define PCFE_AZ_MAX_RD_REQ_SIZE_256 1
+#define PCFE_AZ_MAX_RD_REQ_SIZE_128 0
+#define PCRF_AZ_EN_NO_SNOOP_LBN 11
+#define PCRF_AZ_EN_NO_SNOOP_WIDTH 1
+#define PCRF_AZ_AUX_PWR_PM_EN_LBN 10
+#define PCRF_AZ_AUX_PWR_PM_EN_WIDTH 1
+#define PCRF_AZ_PHAN_FUNC_EN_LBN 9
+#define PCRF_AZ_PHAN_FUNC_EN_WIDTH 1
+#define PCRF_AB_DEV_CAP_REG_RSVD0_LBN 8
+#define PCRF_AB_DEV_CAP_REG_RSVD0_WIDTH 1
+#define PCRF_CZ_EXTENDED_TAG_EN_LBN 8
+#define PCRF_CZ_EXTENDED_TAG_EN_WIDTH 1
+#define PCRF_AZ_MAX_PAYL_SIZE_LBN 5
+#define PCRF_AZ_MAX_PAYL_SIZE_WIDTH 3
+#define PCFE_AZ_MAX_PAYL_SIZE_4096 5
+#define PCFE_AZ_MAX_PAYL_SIZE_2048 4
+#define PCFE_AZ_MAX_PAYL_SIZE_1024 3
+#define PCFE_AZ_MAX_PAYL_SIZE_512 2
+#define PCFE_AZ_MAX_PAYL_SIZE_256 1
+#define PCFE_AZ_MAX_PAYL_SIZE_128 0
+#define PCRF_AZ_EN_RELAX_ORDER_LBN 4
+#define PCRF_AZ_EN_RELAX_ORDER_WIDTH 1
+#define PCRF_AZ_UNSUP_REQ_RPT_EN_LBN 3
+#define PCRF_AZ_UNSUP_REQ_RPT_EN_WIDTH 1
+#define PCRF_AZ_FATAL_ERR_RPT_EN_LBN 2
+#define PCRF_AZ_FATAL_ERR_RPT_EN_WIDTH 1
+#define PCRF_AZ_NONFATAL_ERR_RPT_EN_LBN 1
+#define PCRF_AZ_NONFATAL_ERR_RPT_EN_WIDTH 1
+#define PCRF_AZ_CORR_ERR_RPT_EN_LBN 0
+#define PCRF_AZ_CORR_ERR_RPT_EN_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_DEV_STAT_REG(16bit):
+ * PCIe device status register
+ */
+#define PCR_CZ_DEV_STAT_REG 0x0000007a
+/* sienaa0=pci_f0_config */
+/*
+ * PCR_AB_DEV_STAT_REG(16bit):
+ * PCIe device status register
+ */
+#define PCR_AB_DEV_STAT_REG 0x0000006a
+/* falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AZ_TRNS_PEND_LBN 5
+#define PCRF_AZ_TRNS_PEND_WIDTH 1
+#define PCRF_AZ_AUX_PWR_DET_LBN 4
+#define PCRF_AZ_AUX_PWR_DET_WIDTH 1
+#define PCRF_AZ_UNSUP_REQ_DET_LBN 3
+#define PCRF_AZ_UNSUP_REQ_DET_WIDTH 1
+#define PCRF_AZ_FATAL_ERR_DET_LBN 2
+#define PCRF_AZ_FATAL_ERR_DET_WIDTH 1
+#define PCRF_AZ_NONFATAL_ERR_DET_LBN 1
+#define PCRF_AZ_NONFATAL_ERR_DET_WIDTH 1
+#define PCRF_AZ_CORR_ERR_DET_LBN 0
+#define PCRF_AZ_CORR_ERR_DET_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_LNK_CAP_REG(32bit):
+ * PCIe link capabilities register
+ */
+#define PCR_CZ_LNK_CAP_REG 0x0000007c
+/* sienaa0=pci_f0_config */
+/*
+ * PCR_AB_LNK_CAP_REG(32bit):
+ * PCIe link capabilities register
+ */
+#define PCR_AB_LNK_CAP_REG 0x0000006c
+/* falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AZ_PORT_NUM_LBN 24
+#define PCRF_AZ_PORT_NUM_WIDTH 8
+#define PCRF_CZ_LINK_BWDITH_NOTIF_CAP_LBN 21
+#define PCRF_CZ_LINK_BWDITH_NOTIF_CAP_WIDTH 1
+#define PCRF_CZ_DATA_LINK_ACTIVE_RPT_CAP_LBN 20
+#define PCRF_CZ_DATA_LINK_ACTIVE_RPT_CAP_WIDTH 1
+#define PCRF_CZ_SURPISE_DOWN_RPT_CAP_LBN 19
+#define PCRF_CZ_SURPISE_DOWN_RPT_CAP_WIDTH 1
+#define PCRF_CZ_CLOCK_PWR_MNGMNT_CAP_LBN 18
+#define PCRF_CZ_CLOCK_PWR_MNGMNT_CAP_WIDTH 1
+#define PCRF_AZ_DEF_L1_EXIT_LAT_LBN 15
+#define PCRF_AZ_DEF_L1_EXIT_LAT_WIDTH 3
+#define PCRF_AZ_DEF_L0_EXIT_LATPORT_NUM_LBN 12
+#define PCRF_AZ_DEF_L0_EXIT_LATPORT_NUM_WIDTH 3
+#define PCRF_AZ_AS_LNK_PM_SUPT_LBN 10
+#define PCRF_AZ_AS_LNK_PM_SUPT_WIDTH 2
+#define PCRF_AZ_MAX_LNK_WIDTH_LBN 4
+#define PCRF_AZ_MAX_LNK_WIDTH_WIDTH 6
+#define PCRF_AZ_MAX_LNK_SP_LBN 0
+#define PCRF_AZ_MAX_LNK_SP_WIDTH 4
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_DEV_CTL2_REG(16bit):
+ * PCIe Device Control 2
+ */
+#define PCR_CZ_DEV_CTL2_REG 0x00000098
+/* sienaa0=pci_f0_config */
+
+#define PCRF_CZ_CMPL_TIMEOUT_DIS_CTL_LBN 4
+#define PCRF_CZ_CMPL_TIMEOUT_DIS_CTL_WIDTH 1
+#define PCRF_CZ_CMPL_TIMEOUT_CTL_LBN 0
+#define PCRF_CZ_CMPL_TIMEOUT_CTL_WIDTH 4
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_LNK_STAT2_REG(16bit):
+ * PCIe Link Status 2
+ */
+#define PCR_CZ_LNK_STAT2_REG 0x000000a2
+/* sienaa0=pci_f0_config */
+
+#define PCRF_CZ_CURRENT_DEEMPH_LBN 0
+#define PCRF_CZ_CURRENT_DEEMPH_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_MSIX_NXT_PTR_REG(8bit):
+ * MSIX Capability Next Capability Ptr
+ */
+#define PCR_CZ_MSIX_NXT_PTR_REG 0x000000b1
+/* sienaa0=pci_f0_config */
+/*
+ * PCR_BB_MSIX_NXT_PTR_REG(8bit):
+ * MSIX Capability Next Capability Ptr
+ */
+#define PCR_BB_MSIX_NXT_PTR_REG 0x00000091
+/* falconb0=pci_f0_config */
+
+#define PCRF_BZ_MSIX_NXT_PTR_LBN 0
+#define PCRF_BZ_MSIX_NXT_PTR_WIDTH 8
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_MSIX_CTL_REG(16bit):
+ * MSIX control register
+ */
+#define PCR_CZ_MSIX_CTL_REG 0x000000b2
+/* sienaa0=pci_f0_config */
+/*
+ * PCR_BB_MSIX_CTL_REG(16bit):
+ * MSIX control register
+ */
+#define PCR_BB_MSIX_CTL_REG 0x00000092
+/* falconb0=pci_f0_config */
+
+#define PCRF_BZ_MSIX_EN_LBN 15
+#define PCRF_BZ_MSIX_EN_WIDTH 1
+#define PCRF_BZ_MSIX_FUNC_MASK_LBN 14
+#define PCRF_BZ_MSIX_FUNC_MASK_WIDTH 1
+#define PCRF_BZ_MSIX_TBL_SIZE_LBN 0
+#define PCRF_BZ_MSIX_TBL_SIZE_WIDTH 11
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_AER_UNCORR_ERR_SEV_REG(32bit):
+ * AER Uncorrectable error severity register
+ */
+#define PCR_AZ_AER_UNCORR_ERR_SEV_REG 0x0000010c
+/* sienaa0=pci_f0_config,falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AZ_UNSUPT_REQ_ERR_SEV_LBN 20
+#define PCRF_AZ_UNSUPT_REQ_ERR_SEV_WIDTH 1
+#define PCRF_AZ_ECRC_ERR_SEV_LBN 19
+#define PCRF_AZ_ECRC_ERR_SEV_WIDTH 1
+#define PCRF_AZ_MALF_TLP_SEV_LBN 18
+#define PCRF_AZ_MALF_TLP_SEV_WIDTH 1
+#define PCRF_AZ_RX_OVF_SEV_LBN 17
+#define PCRF_AZ_RX_OVF_SEV_WIDTH 1
+#define PCRF_AZ_UNEXP_COMP_SEV_LBN 16
+#define PCRF_AZ_UNEXP_COMP_SEV_WIDTH 1
+#define PCRF_AZ_COMP_ABRT_SEV_LBN 15
+#define PCRF_AZ_COMP_ABRT_SEV_WIDTH 1
+#define PCRF_AZ_COMP_TIMEOUT_SEV_LBN 14
+#define PCRF_AZ_COMP_TIMEOUT_SEV_WIDTH 1
+#define PCRF_AZ_FC_PROTO_ERR_SEV_LBN 13
+#define PCRF_AZ_FC_PROTO_ERR_SEV_WIDTH 1
+#define PCRF_AZ_PSON_TLP_SEV_LBN 12
+#define PCRF_AZ_PSON_TLP_SEV_WIDTH 1
+#define PCRF_AZ_DL_PROTO_ERR_SEV_LBN 4
+#define PCRF_AZ_DL_PROTO_ERR_SEV_WIDTH 1
+#define PCRF_AB_TRAIN_ERR_SEV_LBN 0
+#define PCRF_AB_TRAIN_ERR_SEV_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_AER_CORR_ERR_STAT_REG(32bit):
+ * AER Correctable error status register
+ */
+#define PCR_AZ_AER_CORR_ERR_STAT_REG 0x00000110
+/* sienaa0=pci_f0_config,falcona0,falconb0=pci_f0_config */
+
+#define PCRF_CZ_ADVSY_NON_FATAL_STAT_LBN 13
+#define PCRF_CZ_ADVSY_NON_FATAL_STAT_WIDTH 1
+#define PCRF_AZ_RPLY_TMR_TOUT_STAT_LBN 12
+#define PCRF_AZ_RPLY_TMR_TOUT_STAT_WIDTH 1
+#define PCRF_AZ_RPLAY_NUM_RO_STAT_LBN 8
+#define PCRF_AZ_RPLAY_NUM_RO_STAT_WIDTH 1
+#define PCRF_AZ_BAD_DLLP_STAT_LBN 7
+#define PCRF_AZ_BAD_DLLP_STAT_WIDTH 1
+#define PCRF_AZ_BAD_TLP_STAT_LBN 6
+#define PCRF_AZ_BAD_TLP_STAT_WIDTH 1
+#define PCRF_AZ_RX_ERR_STAT_LBN 0
+#define PCRF_AZ_RX_ERR_STAT_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_DEVSN_DWORD1_REG(32bit):
+ * Device serial number DWORD0
+ */
+#define PCR_CZ_DEVSN_DWORD1_REG 0x00000148
+/* sienaa0=pci_f0_config */
+
+#define PCRF_CZ_DEVSN_DWORD1_LBN 0
+#define PCRF_CZ_DEVSN_DWORD1_WIDTH 32
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_ARI_CTL_REG(16bit):
+ * ARI Control
+ */
+#define PCR_CZ_ARI_CTL_REG 0x00000156
+/* sienaa0=pci_f0_config */
+
+#define PCRF_CZ_ARI_FN_GRP_LBN 4
+#define PCRF_CZ_ARI_FN_GRP_WIDTH 3
+#define PCRF_CZ_ARI_ACS_FNGRP_EN_LBN 1
+#define PCRF_CZ_ARI_ACS_FNGRP_EN_WIDTH 1
+#define PCRF_CZ_ARI_MFVC_FNGRP_EN_LBN 0
+#define PCRF_CZ_ARI_MFVC_FNGRP_EN_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_SRIOV_CAP_HDR_REG(32bit):
+ * SRIOV capability header register
+ */
+#define PCR_CZ_SRIOV_CAP_HDR_REG 0x00000160
+/* sienaa0=pci_f0_config */
+
+#define PCRF_CZ_SRIOVCAPHDR_NXT_PTR_LBN 20
+#define PCRF_CZ_SRIOVCAPHDR_NXT_PTR_WIDTH 12
+#define PCRF_CZ_SRIOVCAPHDR_VER_LBN 16
+#define PCRF_CZ_SRIOVCAPHDR_VER_WIDTH 4
+#define PCRF_CZ_SRIOVCAPHDR_ID_LBN 0
+#define PCRF_CZ_SRIOVCAPHDR_ID_WIDTH 16
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_SRIOV_INITIALVFS_REG(16bit):
+ * SRIOV Initial VFs
+ */
+#define PCR_CZ_SRIOV_INITIALVFS_REG 0x0000016c
+/* sienaa0=pci_f0_config */
+
+#define PCRF_CZ_VF_INITIALVFS_LBN 0
+#define PCRF_CZ_VF_INITIALVFS_WIDTH 16
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_SRIOV_FN_DPND_LNK_REG(16bit):
+ * SRIOV Function dependency link
+ */
+#define PCR_CZ_SRIOV_FN_DPND_LNK_REG 0x00000172
+/* sienaa0=pci_f0_config */
+
+#define PCRF_CZ_SRIOV_FN_DPND_LNK_LBN 0
+#define PCRF_CZ_SRIOV_FN_DPND_LNK_WIDTH 8
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_SRIOV_1STVF_OFFSET_REG(16bit):
+ * SRIOV First VF Offset
+ */
+#define PCR_CZ_SRIOV_1STVF_OFFSET_REG 0x00000174
+/* sienaa0=pci_f0_config */
+
+#define PCRF_CZ_VF_1STVF_OFFSET_LBN 0
+#define PCRF_CZ_VF_1STVF_OFFSET_WIDTH 16
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_CMD_REG(16bit):
+ * Command register
+ */
+#define PCR_AZ_CMD_REG 0x00000004
+/* falcona0,falconb0=pci_f0_config,sienaa0=pci_f0_config */
+
+#define PCRF_AZ_INTX_DIS_LBN 10
+#define PCRF_AZ_INTX_DIS_WIDTH 1
+#define PCRF_AZ_FB2B_EN_LBN 9
+#define PCRF_AZ_FB2B_EN_WIDTH 1
+#define PCRF_AZ_SERR_EN_LBN 8
+#define PCRF_AZ_SERR_EN_WIDTH 1
+#define PCRF_AZ_IDSEL_CTL_LBN 7
+#define PCRF_AZ_IDSEL_CTL_WIDTH 1
+#define PCRF_AZ_PERR_EN_LBN 6
+#define PCRF_AZ_PERR_EN_WIDTH 1
+#define PCRF_AZ_VGA_PAL_SNP_LBN 5
+#define PCRF_AZ_VGA_PAL_SNP_WIDTH 1
+#define PCRF_AZ_MWI_EN_LBN 4
+#define PCRF_AZ_MWI_EN_WIDTH 1
+#define PCRF_AZ_SPEC_CYC_LBN 3
+#define PCRF_AZ_SPEC_CYC_WIDTH 1
+#define PCRF_AZ_MST_EN_LBN 2
+#define PCRF_AZ_MST_EN_WIDTH 1
+#define PCRF_AZ_MEM_EN_LBN 1
+#define PCRF_AZ_MEM_EN_WIDTH 1
+#define PCRF_AZ_IO_EN_LBN 0
+#define PCRF_AZ_IO_EN_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AB_VPD_CAP_DATA_REG(32bit):
+ * documentation to be written for sum_PC_VPD_CAP_DATA_REG
+ */
+#define PCR_AB_VPD_CAP_DATA_REG 0x000000b4
+/* falcona0,falconb0=pci_f0_config */
+/*
+ * PCR_CZ_VPD_CAP_DATA_REG(32bit):
+ * documentation to be written for sum_PC_VPD_CAP_DATA_REG
+ */
+#define PCR_CZ_VPD_CAP_DATA_REG 0x000000d4
+/* sienaa0=pci_f0_config */
+
+#define PCRF_AZ_VPD_DATA_LBN 0
+#define PCRF_AZ_VPD_DATA_WIDTH 32
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_BAR2_HI_REG(32bit):
+ * Primary function base address register 2 high bits
+ */
+#define PCR_AZ_BAR2_HI_REG 0x0000001c
+/* sienaa0=pci_f0_config,falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AZ_BAR2_HI_LBN 0
+#define PCRF_AZ_BAR2_HI_WIDTH 32
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_SS_VEND_ID_REG(16bit):
+ * Sub-system vendor ID register
+ */
+#define PCR_AZ_SS_VEND_ID_REG 0x0000002c
+/* sienaa0=pci_f0_config,falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AZ_SS_VEND_ID_LBN 0
+#define PCRF_AZ_SS_VEND_ID_WIDTH 16
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_AER_CAP_HDR_REG(32bit):
+ * AER capability header register
+ */
+#define PCR_AZ_AER_CAP_HDR_REG 0x00000100
+/* sienaa0=pci_f0_config,falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AZ_AERCAPHDR_NXT_PTR_LBN 20
+#define PCRF_AZ_AERCAPHDR_NXT_PTR_WIDTH 12
+#define PCRF_AZ_AERCAPHDR_VER_LBN 16
+#define PCRF_AZ_AERCAPHDR_VER_WIDTH 4
+#define PCRF_AZ_AERCAPHDR_ID_LBN 0
+#define PCRF_AZ_AERCAPHDR_ID_WIDTH 16
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_AER_HDR_LOG_REG(128bit):
+ * AER Header log register
+ */
+#define PCR_AZ_AER_HDR_LOG_REG 0x0000011c
+/* sienaa0=pci_f0_config,falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AZ_HDR_LOG_LBN 0
+#define PCRF_AZ_HDR_LOG_WIDTH 128
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_SRIOV_VFSTRIDE_REG(16bit):
+ * SRIOV VF Stride
+ */
+#define PCR_CZ_SRIOV_VFSTRIDE_REG 0x00000176
+/* sienaa0=pci_f0_config */
+
+#define PCRF_CZ_VF_VFSTRIDE_LBN 0
+#define PCRF_CZ_VF_VFSTRIDE_WIDTH 16
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_SRIOV_DEVID_REG(16bit):
+ * SRIOV VF Device ID
+ */
+#define PCR_CZ_SRIOV_DEVID_REG 0x0000017a
+/* sienaa0=pci_f0_config */
+
+#define PCRF_CZ_VF_DEVID_LBN 0
+#define PCRF_CZ_VF_DEVID_WIDTH 16
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_SRIOV_SYS_PAGESZ_REG(32bit):
+ * SRIOV System Page Size
+ */
+#define PCR_CZ_SRIOV_SYS_PAGESZ_REG 0x00000180
+/* sienaa0=pci_f0_config */
+
+#define PCRF_CZ_VF_SYS_PAGESZ_LBN 0
+#define PCRF_CZ_VF_SYS_PAGESZ_WIDTH 16
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_SRIOV_MIBR_SARRAY_OFFSET_REG(32bit):
+ * SRIOV VF Migration State Array Offset
+ */
+#define PCR_CZ_SRIOV_MIBR_SARRAY_OFFSET_REG 0x0000019c
+/* sienaa0=pci_f0_config */
+
+#define PCRF_CZ_VF_MIGR_OFFSET_LBN 3
+#define PCRF_CZ_VF_MIGR_OFFSET_WIDTH 29
+#define PCRF_CZ_VF_MIGR_BIR_LBN 0
+#define PCRF_CZ_VF_MIGR_BIR_WIDTH 3
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_ACK_FREQ_REG(32bit):
+ * ACK frequency register
+ */
+#define PCR_AZ_ACK_FREQ_REG 0x0000070c
+/* sienaa0=pci_f0_config,falcona0,falconb0=pci_f0_config */
+
+#define PCRF_CZ_ALLOW_L1_WITHOUT_L0S_LBN 30
+#define PCRF_CZ_ALLOW_L1_WITHOUT_L0S_WIDTH 1
+#define PCRF_AZ_L1_ENTR_LAT_LBN 27
+#define PCRF_AZ_L1_ENTR_LAT_WIDTH 3
+#define PCRF_AZ_L0_ENTR_LAT_LBN 24
+#define PCRF_AZ_L0_ENTR_LAT_WIDTH 3
+#define PCRF_CZ_COMM_NFTS_LBN 16
+#define PCRF_CZ_COMM_NFTS_WIDTH 8
+#define PCRF_AB_ACK_FREQ_REG_RSVD0_LBN 16
+#define PCRF_AB_ACK_FREQ_REG_RSVD0_WIDTH 3
+#define PCRF_AZ_MAX_FTS_LBN 8
+#define PCRF_AZ_MAX_FTS_WIDTH 8
+#define PCRF_AZ_ACK_FREQ_LBN 0
+#define PCRF_AZ_ACK_FREQ_WIDTH 8
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_DEBUG0_REG(32bit):
+ * Debug register 0
+ */
+#define PCR_AZ_DEBUG0_REG 0x00000728
+/* sienaa0=pci_f0_config,falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AZ_CDI03_LBN 24
+#define PCRF_AZ_CDI03_WIDTH 8
+#define PCRF_AZ_CDI0_LBN 0
+#define PCRF_AZ_CDI0_WIDTH 32
+#define PCRF_AZ_CDI02_LBN 16
+#define PCRF_AZ_CDI02_WIDTH 8
+#define PCRF_AZ_CDI01_LBN 8
+#define PCRF_AZ_CDI01_WIDTH 8
+#define PCRF_AZ_CDI00_LBN 0
+#define PCRF_AZ_CDI00_WIDTH 8
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_VC_XMIT_ARB2_REG(32bit):
+ * VC Transmit Arbitration Register 2
+ */
+#define PCR_CZ_VC_XMIT_ARB2_REG 0x00000744
+/* sienaa0=pci_f0_config */
+
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_CACHE_LSIZE_REG(8bit):
+ * Cache line size
+ */
+#define PCR_AZ_CACHE_LSIZE_REG 0x0000000c
+/* falcona0,falconb0=pci_f0_config,sienaa0=pci_f0_config */
+
+#define PCRF_AZ_CACHE_LSIZE_LBN 0
+#define PCRF_AZ_CACHE_LSIZE_WIDTH 8
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_PM_CAP_ID_REG(8bit):
+ * Power management capability ID
+ */
+#define PCR_AZ_PM_CAP_ID_REG 0x00000040
+/* falcona0,falconb0=pci_f0_config,sienaa0=pci_f0_config */
+
+#define PCRF_AZ_PM_CAP_ID_LBN 0
+#define PCRF_AZ_PM_CAP_ID_WIDTH 8
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_MSI_DAT_REG(16bit):
+ * MSI data register
+ */
+#define PCR_AZ_MSI_DAT_REG 0x0000005c
+/* falcona0,falconb0=pci_f0_config,sienaa0=pci_f0_config */
+
+#define PCRF_AZ_MSI_DAT_LBN 0
+#define PCRF_AZ_MSI_DAT_WIDTH 16
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_FORCE_LNK_REG(24bit):
+ * Port force link register
+ */
+#define PCR_AZ_FORCE_LNK_REG 0x00000708
+/* falcona0,falconb0=pci_f0_config,sienaa0=pci_f0_config */
+
+#define PCRF_AZ_LFS_LBN 16
+#define PCRF_AZ_LFS_WIDTH 6
+#define PCRF_AZ_FL_LBN 15
+#define PCRF_AZ_FL_WIDTH 1
+#define PCRF_AZ_LN_LBN 0
+#define PCRF_AZ_LN_WIDTH 8
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_DEV_CAP2_REG(16bit):
+ * PCIe Device Capabilities 2
+ */
+#define PCR_CZ_DEV_CAP2_REG 0x00000094
+/* sienaa0=pci_f0_config */
+
+#define PCRF_CZ_CMPL_TIMEOUT_DIS_LBN 4
+#define PCRF_CZ_CMPL_TIMEOUT_DIS_WIDTH 1
+#define PCRF_CZ_CMPL_TIMEOUT_LBN 0
+#define PCRF_CZ_CMPL_TIMEOUT_WIDTH 4
+#define PCFE_CZ_CMPL_TIMEOUT_17000_TO_6400MS 14
+#define PCFE_CZ_CMPL_TIMEOUT_4000_TO_1300MS 13
+#define PCFE_CZ_CMPL_TIMEOUT_1000_TO_3500MS 10
+#define PCFE_CZ_CMPL_TIMEOUT_260_TO_900MS 9
+#define PCFE_CZ_CMPL_TIMEOUT_65_TO_210MS 6
+#define PCFE_CZ_CMPL_TIMEOUT_16_TO_55MS 5
+#define PCFE_CZ_CMPL_TIMEOUT_1_TO_10MS 2
+#define PCFE_CZ_CMPL_TIMEOUT_50_TO_100US 1
+#define PCFE_CZ_CMPL_TIMEOUT_DEFAULT 0
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_AER_CAP_CTL_REG(32bit):
+ * AER capability and control register
+ */
+#define PCR_AZ_AER_CAP_CTL_REG 0x00000118
+/* sienaa0=pci_f0_config,falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AZ_ECRC_CHK_EN_LBN 8
+#define PCRF_AZ_ECRC_CHK_EN_WIDTH 1
+#define PCRF_AZ_ECRC_CHK_CAP_LBN 7
+#define PCRF_AZ_ECRC_CHK_CAP_WIDTH 1
+#define PCRF_AZ_ECRC_GEN_EN_LBN 6
+#define PCRF_AZ_ECRC_GEN_EN_WIDTH 1
+#define PCRF_AZ_ECRC_GEN_CAP_LBN 5
+#define PCRF_AZ_ECRC_GEN_CAP_WIDTH 1
+#define PCRF_AZ_1ST_ERR_PTR_LBN 0
+#define PCRF_AZ_1ST_ERR_PTR_WIDTH 5
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_SRIOV_BAR0_REG(32bit):
+ * SRIOV VF Bar0
+ */
+#define PCR_CZ_SRIOV_BAR0_REG 0x00000184
+/* sienaa0=pci_f0_config */
+
+#define PCRF_CZ_VF_BAR_ADDRESS_LBN 0
+#define PCRF_CZ_VF_BAR_ADDRESS_WIDTH 32
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_SRIOV_BAR1_REG(32bit):
+ * SRIOV Bar1
+ */
+#define PCR_CZ_SRIOV_BAR1_REG 0x00000188
+/* sienaa0=pci_f0_config */
+
+/* defined as PCRF_CZ_VF_BAR_ADDRESS_LBN 0; access=rw reset=0x0 */
+/* defined as PCRF_CZ_VF_BAR_ADDRESS_WIDTH 32 */
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_ACK_LAT_TMR_REG(32bit):
+ * ACK latency timer & replay timer register
+ */
+#define PCR_AZ_ACK_LAT_TMR_REG 0x00000700
+/* sienaa0=pci_f0_config,falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AZ_RT_LBN 16
+#define PCRF_AZ_RT_WIDTH 16
+#define PCRF_AZ_ALT_LBN 0
+#define PCRF_AZ_ALT_WIDTH 16
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_SYM_TMR_FLT_MSK_REG(16bit):
+ * Symbol timer and Filter Mask Register
+ */
+#define PCR_CZ_SYM_TMR_FLT_MSK_REG 0x0000071c
+/* sienaa0=pci_f0_config */
+
+#define PCRF_CZ_ET_LBN 11
+#define PCRF_CZ_ET_WIDTH 4
+#define PCRF_CZ_SI1_LBN 8
+#define PCRF_CZ_SI1_WIDTH 3
+#define PCRF_CZ_SI0_LBN 0
+#define PCRF_CZ_SI0_WIDTH 8
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_FLT_MSK_REG(32bit):
+ * Filter Mask Register 2
+ */
+#define PCR_CZ_FLT_MSK_REG 0x00000720
+/* sienaa0=pci_f0_config */
+
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_XCFCC_STAT_REG(24bit):
+ * documentation to be written for sum_PC_XCFCC_STAT_REG
+ */
+#define PCR_AZ_XCFCC_STAT_REG 0x00000738
+/* sienaa0=pci_f0_config,falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AZ_XCDC_LBN 12
+#define PCRF_AZ_XCDC_WIDTH 8
+#define PCRF_AZ_XCHC_LBN 0
+#define PCRF_AZ_XCHC_WIDTH 12
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_MSI_ADR_LO_REG(32bit):
+ * MSI low 32 bits address register
+ */
+#define PCR_AZ_MSI_ADR_LO_REG 0x00000054
+/* falcona0,falconb0=pci_f0_config,sienaa0=pci_f0_config */
+
+#define PCRF_AZ_MSI_ADR_LO_LBN 2
+#define PCRF_AZ_MSI_ADR_LO_WIDTH 30
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AB_SLOT_CAP_REG(32bit):
+ * PCIe slot capabilities register
+ */
+#define PCR_AB_SLOT_CAP_REG 0x00000074
+/* falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AB_SLOT_NUM_LBN 19
+#define PCRF_AB_SLOT_NUM_WIDTH 13
+#define PCRF_AB_SLOT_PWR_LIM_SCL_LBN 15
+#define PCRF_AB_SLOT_PWR_LIM_SCL_WIDTH 2
+#define PCRF_AB_SLOT_PWR_LIM_VAL_LBN 7
+#define PCRF_AB_SLOT_PWR_LIM_VAL_WIDTH 8
+#define PCRF_AB_SLOT_HP_CAP_LBN 6
+#define PCRF_AB_SLOT_HP_CAP_WIDTH 1
+#define PCRF_AB_SLOT_HP_SURP_LBN 5
+#define PCRF_AB_SLOT_HP_SURP_WIDTH 1
+#define PCRF_AB_SLOT_PWR_IND_PRST_LBN 4
+#define PCRF_AB_SLOT_PWR_IND_PRST_WIDTH 1
+#define PCRF_AB_SLOT_ATTN_IND_PRST_LBN 3
+#define PCRF_AB_SLOT_ATTN_IND_PRST_WIDTH 1
+#define PCRF_AB_SLOT_MRL_SENS_PRST_LBN 2
+#define PCRF_AB_SLOT_MRL_SENS_PRST_WIDTH 1
+#define PCRF_AB_SLOT_PWR_CTL_PRST_LBN 1
+#define PCRF_AB_SLOT_PWR_CTL_PRST_WIDTH 1
+#define PCRF_AB_SLOT_ATTN_BUT_PRST_LBN 0
+#define PCRF_AB_SLOT_ATTN_BUT_PRST_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_BAR0_REG(32bit):
+ * Primary function base address register 0
+ */
+#define PCR_AZ_BAR0_REG 0x00000010
+/* sienaa0=pci_f0_config,falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AZ_BAR0_LBN 4
+#define PCRF_AZ_BAR0_WIDTH 28
+#define PCRF_AZ_BAR0_PREF_LBN 3
+#define PCRF_AZ_BAR0_PREF_WIDTH 1
+#define PCRF_AZ_BAR0_TYPE_LBN 1
+#define PCRF_AZ_BAR0_TYPE_WIDTH 2
+#define PCRF_AZ_BAR0_IOM_LBN 0
+#define PCRF_AZ_BAR0_IOM_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_PCIE_CAP_REG(16bit):
+ * PCIe capability register
+ */
+#define PCR_CZ_PCIE_CAP_REG 0x00000072
+/* sienaa0=pci_f0_config */
+/*
+ * PCR_AB_PCIE_CAP_REG(16bit):
+ * PCIe capability register
+ */
+#define PCR_AB_PCIE_CAP_REG 0x00000062
+/* falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AZ_PCIE_INT_MSG_NUM_LBN 9
+#define PCRF_AZ_PCIE_INT_MSG_NUM_WIDTH 5
+#define PCRF_AZ_PCIE_SLOT_IMP_LBN 8
+#define PCRF_AZ_PCIE_SLOT_IMP_WIDTH 1
+#define PCRF_AZ_PCIE_DEV_PORT_TYPE_LBN 4
+#define PCRF_AZ_PCIE_DEV_PORT_TYPE_WIDTH 4
+#define PCRF_AZ_PCIE_CAP_VER_LBN 0
+#define PCRF_AZ_PCIE_CAP_VER_WIDTH 4
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_LNK_CTL2_REG(16bit):
+ * PCIe Link Control 2
+ */
+#define PCR_CZ_LNK_CTL2_REG 0x000000a0
+/* sienaa0=pci_f0_config */
+
+#define PCRF_CZ_POLLING_DEEMPH_LVL_LBN 12
+#define PCRF_CZ_POLLING_DEEMPH_LVL_WIDTH 1
+#define PCRF_CZ_COMPLIANCE_SOS_CTL_LBN 11
+#define PCRF_CZ_COMPLIANCE_SOS_CTL_WIDTH 1
+#define PCRF_CZ_ENTER_MODIFIED_COMPLIANCE_CTL_LBN 10
+#define PCRF_CZ_ENTER_MODIFIED_COMPLIANCE_CTL_WIDTH 1
+#define PCRF_CZ_TRANSMIT_MARGIN_LBN 7
+#define PCRF_CZ_TRANSMIT_MARGIN_WIDTH 3
+#define PCRF_CZ_SELECT_DEEMPH_LBN 6
+#define PCRF_CZ_SELECT_DEEMPH_WIDTH 1
+#define PCRF_CZ_HW_AUTONOMOUS_SPEED_DIS_LBN 5
+#define PCRF_CZ_HW_AUTONOMOUS_SPEED_DIS_WIDTH 1
+#define PCRF_CZ_ENTER_COMPLIANCE_CTL_LBN 4
+#define PCRF_CZ_ENTER_COMPLIANCE_CTL_WIDTH 1
+#define PCRF_CZ_TGT_LNK_SPEED_CTL_LBN 0
+#define PCRF_CZ_TGT_LNK_SPEED_CTL_WIDTH 4
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_MSIX_PBA_BASE_REG(32bit):
+ * MSIX Capability PBA Base
+ */
+#define PCR_CZ_MSIX_PBA_BASE_REG 0x000000b8
+/* sienaa0=pci_f0_config */
+/*
+ * PCR_BB_MSIX_PBA_BASE_REG(32bit):
+ * MSIX Capability PBA Base
+ */
+#define PCR_BB_MSIX_PBA_BASE_REG 0x00000098
+/* falconb0=pci_f0_config */
+
+#define PCRF_BZ_MSIX_PBA_OFF_LBN 3
+#define PCRF_BZ_MSIX_PBA_OFF_WIDTH 29
+#define PCRF_BZ_MSIX_PBA_BIR_LBN 0
+#define PCRF_BZ_MSIX_PBA_BIR_WIDTH 3
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_SRIOV_TOTALVFS_REG(10bit):
+ * SRIOV Total VFs
+ */
+#define PCR_CZ_SRIOV_TOTALVFS_REG 0x0000016e
+/* sienaa0=pci_f0_config */
+
+#define PCRF_CZ_VF_TOTALVFS_LBN 0
+#define PCRF_CZ_VF_TOTALVFS_WIDTH 16
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_DEVSN_DWORD0_REG(32bit):
+ * Device serial number DWORD0
+ */
+#define PCR_CZ_DEVSN_DWORD0_REG 0x00000144
+/* sienaa0=pci_f0_config */
+
+#define PCRF_CZ_DEVSN_DWORD0_LBN 0
+#define PCRF_CZ_DEVSN_DWORD0_WIDTH 32
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_SRIOV_CTL_REG(16bit):
+ * SRIOV Control
+ */
+#define PCR_CZ_SRIOV_CTL_REG 0x00000168
+/* sienaa0=pci_f0_config */
+
+#define PCRF_CZ_VF_ARI_CAP_HRCHY_LBN 4
+#define PCRF_CZ_VF_ARI_CAP_HRCHY_WIDTH 1
+#define PCRF_CZ_VF_MSE_LBN 3
+#define PCRF_CZ_VF_MSE_WIDTH 1
+#define PCRF_CZ_VF_MIGR_INT_EN_LBN 2
+#define PCRF_CZ_VF_MIGR_INT_EN_WIDTH 1
+#define PCRF_CZ_VF_MIGR_EN_LBN 1
+#define PCRF_CZ_VF_MIGR_EN_WIDTH 1
+#define PCRF_CZ_VF_EN_LBN 0
+#define PCRF_CZ_VF_EN_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_SRIOV_NUMVFS_REG(16bit):
+ * SRIOV Number of VFs
+ */
+#define PCR_CZ_SRIOV_NUMVFS_REG 0x00000170
+/* sienaa0=pci_f0_config */
+
+#define PCRF_CZ_VF_NUMVFS_LBN 0
+#define PCRF_CZ_VF_NUMVFS_WIDTH 16
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_SRIOV_SUP_PAGESZ_REG(16bit):
+ * SRIOV Supported Page Sizes
+ */
+#define PCR_CZ_SRIOV_SUP_PAGESZ_REG 0x0000017c
+/* sienaa0=pci_f0_config */
+
+#define PCRF_CZ_VF_SUP_PAGESZ_LBN 0
+#define PCRF_CZ_VF_SUP_PAGESZ_WIDTH 16
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_SRIOV_BAR3_REG(32bit):
+ * SRIOV Bar3
+ */
+#define PCR_CZ_SRIOV_BAR3_REG 0x00000190
+/* sienaa0=pci_f0_config */
+
+/* defined as PCRF_CZ_VF_BAR_ADDRESS_LBN 0; access=rw reset=0x0 */
+/* defined as PCRF_CZ_VF_BAR_ADDRESS_WIDTH 32 */
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_VC0_P_RQ_CTL_REG(32bit):
+ * VC0 Posted Receive Queue Control
+ */
+#define PCR_CZ_VC0_P_RQ_CTL_REG 0x00000748
+/* sienaa0=pci_f0_config */
+
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_PM_CAP_REG(16bit):
+ * Power management capabilities register
+ */
+#define PCR_AZ_PM_CAP_REG 0x00000042
+/* falcona0,falconb0=pci_f0_config,sienaa0=pci_f0_config */
+
+#define PCRF_AZ_PM_PME_SUPT_LBN 11
+#define PCRF_AZ_PM_PME_SUPT_WIDTH 5
+#define PCRF_AZ_PM_D2_SUPT_LBN 10
+#define PCRF_AZ_PM_D2_SUPT_WIDTH 1
+#define PCRF_AZ_PM_D1_SUPT_LBN 9
+#define PCRF_AZ_PM_D1_SUPT_WIDTH 1
+#define PCRF_AZ_PM_AUX_CURR_LBN 6
+#define PCRF_AZ_PM_AUX_CURR_WIDTH 3
+#define PCRF_AZ_PM_DSI_LBN 5
+#define PCRF_AZ_PM_DSI_WIDTH 1
+#define PCRF_AZ_PM_PME_CLK_LBN 3
+#define PCRF_AZ_PM_PME_CLK_WIDTH 1
+#define PCRF_AZ_PM_PME_VER_LBN 0
+#define PCRF_AZ_PM_PME_VER_WIDTH 3
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AB_LNK_CTL_REG(16bit):
+ * PCIe link control register
+ */
+#define PCR_AB_LNK_CTL_REG 0x00000070
+/* falcona0,falconb0=pci_f0_config */
+/*
+ * PCR_CZ_LNK_CTL_REG(16bit):
+ * PCIe link control register
+ */
+#define PCR_CZ_LNK_CTL_REG 0x00000080
+/* sienaa0=pci_f0_config */
+
+#define PCRF_AZ_EXT_SYNC_LBN 7
+#define PCRF_AZ_EXT_SYNC_WIDTH 1
+#define PCRF_AZ_COMM_CLK_CFG_LBN 6
+#define PCRF_AZ_COMM_CLK_CFG_WIDTH 1
+#define PCRF_AB_LNK_CTL_REG_RSVD0_LBN 5
+#define PCRF_AB_LNK_CTL_REG_RSVD0_WIDTH 1
+#define PCRF_CZ_LNK_RETRAIN_LBN 5
+#define PCRF_CZ_LNK_RETRAIN_WIDTH 1
+#define PCRF_AZ_LNK_DIS_LBN 4
+#define PCRF_AZ_LNK_DIS_WIDTH 1
+#define PCRF_AZ_RD_COM_BDRY_LBN 3
+#define PCRF_AZ_RD_COM_BDRY_WIDTH 1
+#define PCRF_AZ_ACT_ST_LNK_PM_CTL_LBN 0
+#define PCRF_AZ_ACT_ST_LNK_PM_CTL_WIDTH 2
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_BB_MSIX_TBL_BASE_REG(32bit):
+ * MSIX Capability Vector Table Base
+ */
+#define PCR_BB_MSIX_TBL_BASE_REG 0x00000094
+/* falconb0=pci_f0_config */
+/*
+ * PCR_CZ_MSIX_TBL_BASE_REG(32bit):
+ * MSIX Capability Vector Table Base
+ */
+#define PCR_CZ_MSIX_TBL_BASE_REG 0x000000b4
+/* sienaa0=pci_f0_config */
+
+#define PCRF_BZ_MSIX_TBL_OFF_LBN 3
+#define PCRF_BZ_MSIX_TBL_OFF_WIDTH 29
+#define PCRF_BZ_MSIX_TBL_BIR_LBN 0
+#define PCRF_BZ_MSIX_TBL_BIR_WIDTH 3
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_XPFCC_STAT_REG(24bit):
+ * documentation to be written for sum_PC_XPFCC_STAT_REG
+ */
+#define PCR_AZ_XPFCC_STAT_REG 0x00000730
+/* falcona0,falconb0=pci_f0_config,sienaa0=pci_f0_config */
+
+#define PCRF_AZ_XPDC_LBN 12
+#define PCRF_AZ_XPDC_WIDTH 8
+#define PCRF_AZ_XPHC_LBN 0
+#define PCRF_AZ_XPHC_WIDTH 12
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_XNPFCC_STAT_REG(24bit):
+ * documentation to be written for sum_PC_XNPFCC_STAT_REG
+ */
+#define PCR_AZ_XNPFCC_STAT_REG 0x00000734
+/* falcona0,falconb0=pci_f0_config,sienaa0=pci_f0_config */
+
+#define PCRF_AZ_XNPDC_LBN 12
+#define PCRF_AZ_XNPDC_WIDTH 8
+#define PCRF_AZ_XNPHC_LBN 0
+#define PCRF_AZ_XNPHC_WIDTH 12
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_MSIX_CAP_ID_REG(8bit):
+ * MSIX Capability ID
+ */
+#define PCR_CZ_MSIX_CAP_ID_REG 0x000000b0
+/* sienaa0=pci_f0_config */
+/*
+ * PCR_BB_MSIX_CAP_ID_REG(8bit):
+ * MSIX Capability ID
+ */
+#define PCR_BB_MSIX_CAP_ID_REG 0x00000090
+/* falconb0=pci_f0_config */
+
+#define PCRF_BZ_MSIX_CAP_ID_LBN 0
+#define PCRF_BZ_MSIX_CAP_ID_WIDTH 8
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_DEVSN_CAP_HDR_REG(32bit):
+ * Device serial number capability header register
+ */
+#define PCR_CZ_DEVSN_CAP_HDR_REG 0x00000140
+/* sienaa0=pci_f0_config */
+
+#define PCRF_CZ_DEVSNCAPHDR_NXT_PTR_LBN 20
+#define PCRF_CZ_DEVSNCAPHDR_NXT_PTR_WIDTH 12
+#define PCRF_CZ_DEVSNCAPHDR_VER_LBN 16
+#define PCRF_CZ_DEVSNCAPHDR_VER_WIDTH 4
+#define PCRF_CZ_DEVSNCAPHDR_ID_LBN 0
+#define PCRF_CZ_DEVSNCAPHDR_ID_WIDTH 16
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_ARI_CAP_HDR_REG(32bit):
+ * ARI capability header register
+ */
+#define PCR_CZ_ARI_CAP_HDR_REG 0x00000150
+/* sienaa0=pci_f0_config */
+
+#define PCRF_CZ_ARICAPHDR_NXT_PTR_LBN 20
+#define PCRF_CZ_ARICAPHDR_NXT_PTR_WIDTH 12
+#define PCRF_CZ_ARICAPHDR_VER_LBN 16
+#define PCRF_CZ_ARICAPHDR_VER_WIDTH 4
+#define PCRF_CZ_ARICAPHDR_ID_LBN 0
+#define PCRF_CZ_ARICAPHDR_ID_WIDTH 16
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_SRIOV_BAR4_REG(32bit):
+ * SRIOV Bar4
+ */
+#define PCR_CZ_SRIOV_BAR4_REG 0x00000194
+/* sienaa0=pci_f0_config */
+
+/* defined as PCRF_CZ_VF_BAR_ADDRESS_LBN 0; access=rw reset=0x0 */
+/* defined as PCRF_CZ_VF_BAR_ADDRESS_WIDTH 32 */
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_VC0_C_RQ_CTL_REG(32bit):
+ * VC0 Completion Receive Queue Control
+ */
+#define PCR_CZ_VC0_C_RQ_CTL_REG 0x00000750
+/* sienaa0=pci_f0_config */
+
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_LN_SKEW_REG(32bit):
+ * Lane skew register
+ */
+#define PCR_AZ_LN_SKEW_REG 0x00000714
+/* falcona0,falconb0=pci_f0_config,sienaa0=pci_f0_config */
+
+#define PCRF_AZ_DIS_LBN 31
+#define PCRF_AZ_DIS_WIDTH 1
+#define PCRF_AB_RST_LBN 30
+#define PCRF_AB_RST_WIDTH 1
+#define PCRF_AZ_AD_LBN 25
+#define PCRF_AZ_AD_WIDTH 1
+#define PCRF_AZ_FCD_LBN 24
+#define PCRF_AZ_FCD_WIDTH 1
+#define PCRF_AZ_LS2_LBN 16
+#define PCRF_AZ_LS2_WIDTH 8
+#define PCRF_AZ_LS1_LBN 8
+#define PCRF_AZ_LS1_WIDTH 8
+#define PCRF_AZ_LS0_LBN 0
+#define PCRF_AZ_LS0_WIDTH 8
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_SRIOV_CAP_REG(32bit):
+ * SRIOV Capabilities
+ */
+#define PCR_CZ_SRIOV_CAP_REG 0x00000164
+/* sienaa0=pci_f0_config */
+
+#define PCRF_CZ_VF_MIGR_INT_MSG_NUM_LBN 21
+#define PCRF_CZ_VF_MIGR_INT_MSG_NUM_WIDTH 11
+#define PCRF_CZ_VF_MIGR_CAP_LBN 0
+#define PCRF_CZ_VF_MIGR_CAP_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_SRIOV_BAR5_REG(32bit):
+ * SRIOV Bar5
+ */
+#define PCR_CZ_SRIOV_BAR5_REG 0x00000198
+/* sienaa0=pci_f0_config */
+
+/* defined as PCRF_CZ_VF_BAR_ADDRESS_LBN 0; access=rw reset=0x0 */
+/* defined as PCRF_CZ_VF_BAR_ADDRESS_WIDTH 32 */
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_DEBUG1_REG(32bit):
+ * Debug register 1
+ */
+#define PCR_AZ_DEBUG1_REG 0x0000072c
+/* sienaa0=pci_f0_config,falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AZ_CDI13_LBN 24
+#define PCRF_AZ_CDI13_WIDTH 8
+#define PCRF_AZ_CDI1_LBN 0
+#define PCRF_AZ_CDI1_WIDTH 32
+#define PCRF_AZ_CDI12_LBN 16
+#define PCRF_AZ_CDI12_WIDTH 8
+#define PCRF_AZ_CDI11_LBN 8
+#define PCRF_AZ_CDI11_WIDTH 8
+#define PCRF_AZ_CDI10_LBN 0
+#define PCRF_AZ_CDI10_WIDTH 8
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_PHY_STAT_REG(32bit):
+ * PHY status register
+ */
+#define PCR_CZ_PHY_STAT_REG 0x00000810
+/* sienaa0=pci_f0_config */
+/*
+ * PCR_AB_PHY_STAT_REG(8bit):
+ * PHY status register
+ */
+#define PCR_AB_PHY_STAT_REG 0x00000720
+/* falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AZ_SSL_LBN 3
+#define PCRF_AZ_SSL_WIDTH 1
+#define PCRF_AZ_SSR_LBN 2
+#define PCRF_AZ_SSR_WIDTH 1
+#define PCRF_AZ_SSCL_LBN 1
+#define PCRF_AZ_SSCL_WIDTH 1
+#define PCRF_AZ_SSCD_LBN 0
+#define PCRF_AZ_SSCD_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_GEN2_REG(32bit):
+ * Gen2 Register
+ */
+#define PCR_CZ_GEN2_REG 0x0000080c
+/* sienaa0=pci_f0_config */
+
+#define PCRF_CZ_SET_DE_EMPHASIS_LBN 20
+#define PCRF_CZ_SET_DE_EMPHASIS_WIDTH 1
+#define PCRF_CZ_CFG_TX_COMPLIANCE_LBN 19
+#define PCRF_CZ_CFG_TX_COMPLIANCE_WIDTH 1
+#define PCRF_CZ_CFG_TX_SWING_LBN 18
+#define PCRF_CZ_CFG_TX_SWING_WIDTH 1
+#define PCRF_CZ_DIR_SPEED_CHANGE_LBN 17
+#define PCRF_CZ_DIR_SPEED_CHANGE_WIDTH 1
+#define PCRF_CZ_LANE_ENABLE_LBN 8
+#define PCRF_CZ_LANE_ENABLE_WIDTH 9
+#define PCRF_CZ_NUM_FTS_LBN 0
+#define PCRF_CZ_NUM_FTS_WIDTH 8
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_BAR2_LO_REG(32bit):
+ * Primary function base address register 2 low bits
+ */
+#define PCR_AZ_BAR2_LO_REG 0x00000018
+/* falcona0,falconb0=pci_f0_config,sienaa0=pci_f0_config */
+
+#define PCRF_AZ_BAR2_LO_LBN 4
+#define PCRF_AZ_BAR2_LO_WIDTH 28
+#define PCRF_AZ_BAR2_PREF_LBN 3
+#define PCRF_AZ_BAR2_PREF_WIDTH 1
+#define PCRF_AZ_BAR2_TYPE_LBN 1
+#define PCRF_AZ_BAR2_TYPE_WIDTH 2
+#define PCRF_AZ_BAR2_IOM_LBN 0
+#define PCRF_AZ_BAR2_IOM_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_PM_NXT_PTR_REG(8bit):
+ * Power management next item pointer
+ */
+#define PCR_AZ_PM_NXT_PTR_REG 0x00000041
+/* falcona0,falconb0=pci_f0_config,sienaa0=pci_f0_config */
+
+#define PCRF_AZ_PM_NXT_PTR_LBN 0
+#define PCRF_AZ_PM_NXT_PTR_WIDTH 8
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AB_SLOT_CTL_REG(16bit):
+ * PCIe slot control register
+ */
+#define PCR_AB_SLOT_CTL_REG 0x00000078
+/* falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AB_SLOT_PWR_CTLR_CTL_LBN 10
+#define PCRF_AB_SLOT_PWR_CTLR_CTL_WIDTH 1
+#define PCRF_AB_SLOT_PWR_IND_CTL_LBN 8
+#define PCRF_AB_SLOT_PWR_IND_CTL_WIDTH 2
+#define PCRF_AB_SLOT_ATT_IND_CTL_LBN 6
+#define PCRF_AB_SLOT_ATT_IND_CTL_WIDTH 2
+#define PCRF_AB_SLOT_HP_INT_EN_LBN 5
+#define PCRF_AB_SLOT_HP_INT_EN_WIDTH 1
+#define PCRF_AB_SLOT_CMD_COMP_INT_EN_LBN 4
+#define PCRF_AB_SLOT_CMD_COMP_INT_EN_WIDTH 1
+#define PCRF_AB_SLOT_PRES_DET_CHG_EN_LBN 3
+#define PCRF_AB_SLOT_PRES_DET_CHG_EN_WIDTH 1
+#define PCRF_AB_SLOT_MRL_SENS_CHG_EN_LBN 2
+#define PCRF_AB_SLOT_MRL_SENS_CHG_EN_WIDTH 1
+#define PCRF_AB_SLOT_PWR_FLTDET_EN_LBN 1
+#define PCRF_AB_SLOT_PWR_FLTDET_EN_WIDTH 1
+#define PCRF_AB_SLOT_ATTN_BUT_EN_LBN 0
+#define PCRF_AB_SLOT_ATTN_BUT_EN_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AB_VPD_CAP_ID_REG(8bit):
+ * VPD data register
+ */
+#define PCR_AB_VPD_CAP_ID_REG 0x000000b0
+/* falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AB_VPD_CAP_ID_LBN 0
+#define PCRF_AB_VPD_CAP_ID_WIDTH 8
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AB_VPD_NXT_PTR_REG(8bit):
+ * VPD next item pointer
+ */
+#define PCR_AB_VPD_NXT_PTR_REG 0x000000b1
+/* falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AB_VPD_NXT_PTR_LBN 0
+#define PCRF_AB_VPD_NXT_PTR_WIDTH 8
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_AER_UNCORR_ERR_STAT_REG(32bit):
+ * AER Uncorrectable error status register
+ */
+#define PCR_AZ_AER_UNCORR_ERR_STAT_REG 0x00000104
+/* falcona0,falconb0=pci_f0_config,sienaa0=pci_f0_config */
+
+#define PCRF_AZ_UNSUPT_REQ_ERR_STAT_LBN 20
+#define PCRF_AZ_UNSUPT_REQ_ERR_STAT_WIDTH 1
+#define PCRF_AZ_ECRC_ERR_STAT_LBN 19
+#define PCRF_AZ_ECRC_ERR_STAT_WIDTH 1
+#define PCRF_AZ_MALF_TLP_STAT_LBN 18
+#define PCRF_AZ_MALF_TLP_STAT_WIDTH 1
+#define PCRF_AZ_RX_OVF_STAT_LBN 17
+#define PCRF_AZ_RX_OVF_STAT_WIDTH 1
+#define PCRF_AZ_UNEXP_COMP_STAT_LBN 16
+#define PCRF_AZ_UNEXP_COMP_STAT_WIDTH 1
+#define PCRF_AZ_COMP_ABRT_STAT_LBN 15
+#define PCRF_AZ_COMP_ABRT_STAT_WIDTH 1
+#define PCRF_AZ_COMP_TIMEOUT_STAT_LBN 14
+#define PCRF_AZ_COMP_TIMEOUT_STAT_WIDTH 1
+#define PCRF_AZ_FC_PROTO_ERR_STAT_LBN 13
+#define PCRF_AZ_FC_PROTO_ERR_STAT_WIDTH 1
+#define PCRF_AZ_PSON_TLP_STAT_LBN 12
+#define PCRF_AZ_PSON_TLP_STAT_WIDTH 1
+#define PCRF_AZ_DL_PROTO_ERR_STAT_LBN 4
+#define PCRF_AZ_DL_PROTO_ERR_STAT_WIDTH 1
+#define PCRF_AB_TRAIN_ERR_STAT_LBN 0
+#define PCRF_AB_TRAIN_ERR_STAT_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_STAT_REG(16bit):
+ * Status register
+ */
+#define PCR_AZ_STAT_REG 0x00000006
+/* sienaa0=pci_f0_config,falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AZ_DET_PERR_LBN 15
+#define PCRF_AZ_DET_PERR_WIDTH 1
+#define PCRF_AZ_SIG_SERR_LBN 14
+#define PCRF_AZ_SIG_SERR_WIDTH 1
+#define PCRF_AZ_GOT_MABRT_LBN 13
+#define PCRF_AZ_GOT_MABRT_WIDTH 1
+#define PCRF_AZ_GOT_TABRT_LBN 12
+#define PCRF_AZ_GOT_TABRT_WIDTH 1
+#define PCRF_AZ_SIG_TABRT_LBN 11
+#define PCRF_AZ_SIG_TABRT_WIDTH 1
+#define PCRF_AZ_DEVSEL_TIM_LBN 9
+#define PCRF_AZ_DEVSEL_TIM_WIDTH 2
+#define PCRF_AZ_MDAT_PERR_LBN 8
+#define PCRF_AZ_MDAT_PERR_WIDTH 1
+#define PCRF_AZ_FB2B_CAP_LBN 7
+#define PCRF_AZ_FB2B_CAP_WIDTH 1
+#define PCRF_AZ_66MHZ_CAP_LBN 5
+#define PCRF_AZ_66MHZ_CAP_WIDTH 1
+#define PCRF_AZ_CAP_LIST_LBN 4
+#define PCRF_AZ_CAP_LIST_WIDTH 1
+#define PCRF_AZ_INTX_STAT_LBN 3
+#define PCRF_AZ_INTX_STAT_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_BAR4_HI_REG(32bit):
+ * Primary function base address register 2 high bits
+ */
+#define PCR_CZ_BAR4_HI_REG 0x00000024
+/* sienaa0=pci_f0_config */
+
+#define PCRF_CZ_BAR4_HI_LBN 0
+#define PCRF_CZ_BAR4_HI_WIDTH 32
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_LNK_STAT_REG(16bit):
+ * PCIe link status register
+ */
+#define PCR_CZ_LNK_STAT_REG 0x00000082
+/* sienaa0=pci_f0_config */
+/*
+ * PCR_AB_LNK_STAT_REG(16bit):
+ * PCIe link status register
+ */
+#define PCR_AB_LNK_STAT_REG 0x00000072
+/* falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AZ_SLOT_CLK_CFG_LBN 12
+#define PCRF_AZ_SLOT_CLK_CFG_WIDTH 1
+#define PCRF_AZ_LNK_TRAIN_LBN 11
+#define PCRF_AZ_LNK_TRAIN_WIDTH 1
+#define PCRF_AB_TRAIN_ERR_LBN 10
+#define PCRF_AB_TRAIN_ERR_WIDTH 1
+#define PCRF_AZ_LNK_WIDTH_LBN 4
+#define PCRF_AZ_LNK_WIDTH_WIDTH 6
+#define PCRF_AZ_LNK_SP_LBN 0
+#define PCRF_AZ_LNK_SP_WIDTH 4
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_AER_CORR_ERR_MASK_REG(32bit):
+ * AER Correctable error status register
+ */
+#define PCR_AZ_AER_CORR_ERR_MASK_REG 0x00000114
+/* falcona0,falconb0=pci_f0_config,sienaa0=pci_f0_config */
+
+#define PCRF_CZ_ADVSY_NON_FATAL_MASK_LBN 13
+#define PCRF_CZ_ADVSY_NON_FATAL_MASK_WIDTH 1
+#define PCRF_AZ_RPLY_TMR_TOUT_MASK_LBN 12
+#define PCRF_AZ_RPLY_TMR_TOUT_MASK_WIDTH 1
+#define PCRF_AZ_RPLAY_NUM_RO_MASK_LBN 8
+#define PCRF_AZ_RPLAY_NUM_RO_MASK_WIDTH 1
+#define PCRF_AZ_BAD_DLLP_MASK_LBN 7
+#define PCRF_AZ_BAD_DLLP_MASK_WIDTH 1
+#define PCRF_AZ_BAD_TLP_MASK_LBN 6
+#define PCRF_AZ_BAD_TLP_MASK_WIDTH 1
+#define PCRF_AZ_RX_ERR_MASK_LBN 0
+#define PCRF_AZ_RX_ERR_MASK_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_SYM_NUM_REG(16bit):
+ * Symbol number register
+ */
+#define PCR_AZ_SYM_NUM_REG 0x00000718
+/* falcona0,falconb0=pci_f0_config,sienaa0=pci_f0_config */
+
+#define PCRF_CZ_MAX_FUNCTIONS_LBN 29
+#define PCRF_CZ_MAX_FUNCTIONS_WIDTH 3
+#define PCRF_CZ_FC_WATCHDOG_TMR_LBN 24
+#define PCRF_CZ_FC_WATCHDOG_TMR_WIDTH 5
+#define PCRF_CZ_ACK_NAK_TMR_MOD_LBN 19
+#define PCRF_CZ_ACK_NAK_TMR_MOD_WIDTH 5
+#define PCRF_CZ_REPLAY_TMR_MOD_LBN 14
+#define PCRF_CZ_REPLAY_TMR_MOD_WIDTH 5
+#define PCRF_AB_ES_LBN 12
+#define PCRF_AB_ES_WIDTH 3
+#define PCRF_AB_SYM_NUM_REG_RSVD0_LBN 11
+#define PCRF_AB_SYM_NUM_REG_RSVD0_WIDTH 1
+#define PCRF_CZ_NUM_SKP_SYMS_LBN 8
+#define PCRF_CZ_NUM_SKP_SYMS_WIDTH 3
+#define PCRF_AB_TS2_LBN 4
+#define PCRF_AB_TS2_WIDTH 4
+#define PCRF_AZ_TS1_LBN 0
+#define PCRF_AZ_TS1_WIDTH 4
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_Q_STAT_REG(8bit):
+ * documentation to be written for sum_PC_Q_STAT_REG
+ */
+#define PCR_AZ_Q_STAT_REG 0x0000073c
+/* falcona0,falconb0=pci_f0_config,sienaa0=pci_f0_config */
+
+#define PCRF_AZ_RQNE_LBN 2
+#define PCRF_AZ_RQNE_WIDTH 1
+#define PCRF_AZ_XRNE_LBN 1
+#define PCRF_AZ_XRNE_WIDTH 1
+#define PCRF_AZ_RCNR_LBN 0
+#define PCRF_AZ_RCNR_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_VPD_CAP_CTL_REG(8bit):
+ * VPD control and capabilities register
+ */
+#define PCR_CZ_VPD_CAP_CTL_REG 0x000000d0
+/* sienaa0=pci_f0_config */
+
+#define PCRF_CZ_VPD_FLAG_LBN 31
+#define PCRF_CZ_VPD_FLAG_WIDTH 1
+#define PCRF_CZ_VPD_ADDR_LBN 16
+#define PCRF_CZ_VPD_ADDR_WIDTH 15
+#define PCRF_CZ_VPD_NXT_PTR_LBN 8
+#define PCRF_CZ_VPD_NXT_PTR_WIDTH 8
+#define PCRF_CZ_VPD_CAP_ID_LBN 0
+#define PCRF_CZ_VPD_CAP_ID_WIDTH 8
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_AER_UNCORR_ERR_MASK_REG(32bit):
+ * AER Uncorrectable error mask register
+ */
+#define PCR_AZ_AER_UNCORR_ERR_MASK_REG 0x00000108
+/* sienaa0=pci_f0_config,falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AZ_UNSUPT_REQ_ERR_MASK_LBN 20
+#define PCRF_AZ_UNSUPT_REQ_ERR_MASK_WIDTH 1
+#define PCRF_AZ_ECRC_ERR_MASK_LBN 19
+#define PCRF_AZ_ECRC_ERR_MASK_WIDTH 1
+#define PCRF_AZ_MALF_TLP_MASK_LBN 18
+#define PCRF_AZ_MALF_TLP_MASK_WIDTH 1
+#define PCRF_AZ_RX_OVF_MASK_LBN 17
+#define PCRF_AZ_RX_OVF_MASK_WIDTH 1
+#define PCRF_AZ_UNEXP_COMP_MASK_LBN 16
+#define PCRF_AZ_UNEXP_COMP_MASK_WIDTH 1
+#define PCRF_AZ_COMP_ABRT_MASK_LBN 15
+#define PCRF_AZ_COMP_ABRT_MASK_WIDTH 1
+#define PCRF_AZ_COMP_TIMEOUT_MASK_LBN 14
+#define PCRF_AZ_COMP_TIMEOUT_MASK_WIDTH 1
+#define PCRF_AZ_FC_PROTO_ERR_MASK_LBN 13
+#define PCRF_AZ_FC_PROTO_ERR_MASK_WIDTH 1
+#define PCRF_AZ_PSON_TLP_MASK_LBN 12
+#define PCRF_AZ_PSON_TLP_MASK_WIDTH 1
+#define PCRF_AZ_DL_PROTO_ERR_MASK_LBN 4
+#define PCRF_AZ_DL_PROTO_ERR_MASK_WIDTH 1
+#define PCRF_AB_TRAIN_ERR_MASK_LBN 0
+#define PCRF_AB_TRAIN_ERR_MASK_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_ARI_CAP_REG(16bit):
+ * ARI Capabilities
+ */
+#define PCR_CZ_ARI_CAP_REG 0x00000154
+/* sienaa0=pci_f0_config */
+
+#define PCRF_CZ_ARI_NXT_FN_NUM_LBN 8
+#define PCRF_CZ_ARI_NXT_FN_NUM_WIDTH 8
+#define PCRF_CZ_ARI_ACS_FNGRP_CAP_LBN 1
+#define PCRF_CZ_ARI_ACS_FNGRP_CAP_WIDTH 1
+#define PCRF_CZ_ARI_MFVC_FNGRP_CAP_LBN 0
+#define PCRF_CZ_ARI_MFVC_FNGRP_CAP_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_SRIOV_STAT_REG(16bit):
+ * SRIOV Status
+ */
+#define PCR_CZ_SRIOV_STAT_REG 0x0000016a
+/* sienaa0=pci_f0_config */
+
+#define PCRF_CZ_VF_MIGR_STAT_LBN 0
+#define PCRF_CZ_VF_MIGR_STAT_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_OTHER_MSG_REG(32bit):
+ * Other message register
+ */
+#define PCR_AZ_OTHER_MSG_REG 0x00000704
+/* sienaa0=pci_f0_config,falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AZ_OM_CRPT3_LBN 24
+#define PCRF_AZ_OM_CRPT3_WIDTH 8
+#define PCRF_AZ_OM_CRPT2_LBN 16
+#define PCRF_AZ_OM_CRPT2_WIDTH 8
+#define PCRF_AZ_OM_CRPT1_LBN 8
+#define PCRF_AZ_OM_CRPT1_WIDTH 8
+#define PCRF_AZ_OM_CRPT0_LBN 0
+#define PCRF_AZ_OM_CRPT0_WIDTH 8
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AB_SLOT_STAT_REG(16bit):
+ * PCIe slot status register
+ */
+#define PCR_AB_SLOT_STAT_REG 0x0000007a
+/* falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AB_PRES_DET_ST_LBN 6
+#define PCRF_AB_PRES_DET_ST_WIDTH 1
+#define PCRF_AB_MRL_SENS_ST_LBN 5
+#define PCRF_AB_MRL_SENS_ST_WIDTH 1
+#define PCRF_AB_SLOT_PWR_IND_LBN 4
+#define PCRF_AB_SLOT_PWR_IND_WIDTH 1
+#define PCRF_AB_SLOT_ATTN_IND_LBN 3
+#define PCRF_AB_SLOT_ATTN_IND_WIDTH 1
+#define PCRF_AB_SLOT_MRL_SENS_LBN 2
+#define PCRF_AB_SLOT_MRL_SENS_WIDTH 1
+#define PCRF_AB_PWR_FLTDET_LBN 1
+#define PCRF_AB_PWR_FLTDET_WIDTH 1
+#define PCRF_AB_ATTN_BUTDET_LBN 0
+#define PCRF_AB_ATTN_BUTDET_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_SRIOV_BAR2_REG(32bit):
+ * SRIOV Bar2
+ */
+#define PCR_CZ_SRIOV_BAR2_REG 0x0000018c
+/* sienaa0=pci_f0_config */
+
+/* defined as PCRF_CZ_VF_BAR_ADDRESS_LBN 0; access=rw reset=0x0 */
+/* defined as PCRF_CZ_VF_BAR_ADDRESS_WIDTH 32 */
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_PORT_LNK_CTL_REG(32bit):
+ * Port link control register
+ */
+#define PCR_AZ_PORT_LNK_CTL_REG 0x00000710
+/* sienaa0=pci_f0_config,falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AZ_LRE_LBN 27
+#define PCRF_AZ_LRE_WIDTH 1
+#define PCRF_AZ_ESYNC_LBN 26
+#define PCRF_AZ_ESYNC_WIDTH 1
+#define PCRF_AZ_CRPT_LBN 25
+#define PCRF_AZ_CRPT_WIDTH 1
+#define PCRF_AZ_XB_LBN 24
+#define PCRF_AZ_XB_WIDTH 1
+#define PCRF_AZ_LC_LBN 16
+#define PCRF_AZ_LC_WIDTH 6
+#define PCRF_AZ_LDR_LBN 8
+#define PCRF_AZ_LDR_WIDTH 4
+#define PCRF_AZ_FLM_LBN 7
+#define PCRF_AZ_FLM_WIDTH 1
+#define PCRF_AZ_LKD_LBN 6
+#define PCRF_AZ_LKD_WIDTH 1
+#define PCRF_AZ_DLE_LBN 5
+#define PCRF_AZ_DLE_WIDTH 1
+#define PCRF_AZ_PORT_LNK_CTL_REG_RSVD0_LBN 4
+#define PCRF_AZ_PORT_LNK_CTL_REG_RSVD0_WIDTH 1
+#define PCRF_AZ_RA_LBN 3
+#define PCRF_AZ_RA_WIDTH 1
+#define PCRF_AZ_LE_LBN 2
+#define PCRF_AZ_LE_WIDTH 1
+#define PCRF_AZ_SD_LBN 1
+#define PCRF_AZ_SD_WIDTH 1
+#define PCRF_AZ_OMR_LBN 0
+#define PCRF_AZ_OMR_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_VC_XMIT_ARB1_REG(32bit):
+ * VC Transmit Arbitration Register 1
+ */
+#define PCR_CZ_VC_XMIT_ARB1_REG 0x00000740
+/* sienaa0=pci_f0_config */
+
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_VC0_NP_RQ_CTL_REG(32bit):
+ * VC0 Non-Posted Receive Queue Control
+ */
+#define PCR_CZ_VC0_NP_RQ_CTL_REG 0x0000074c
+/* sienaa0=pci_f0_config */
+
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_PHY_CTL_REG(32bit):
+ * PHY control register
+ */
+#define PCR_CZ_PHY_CTL_REG 0x00000814
+/* sienaa0=pci_f0_config */
+/*
+ * PCR_AB_PHY_CTL_REG(32bit):
+ * PHY control register
+ */
+#define PCR_AB_PHY_CTL_REG 0x00000724
+/* falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AZ_BD_LBN 31
+#define PCRF_AZ_BD_WIDTH 1
+#define PCRF_AZ_CDS_LBN 30
+#define PCRF_AZ_CDS_WIDTH 1
+#define PCRF_AZ_DWRAP_LB_LBN 29
+#define PCRF_AZ_DWRAP_LB_WIDTH 1
+#define PCRF_AZ_EBD_LBN 28
+#define PCRF_AZ_EBD_WIDTH 1
+#define PCRF_AZ_SNR_LBN 27
+#define PCRF_AZ_SNR_WIDTH 1
+#define PCRF_AZ_RX_NOT_DET_LBN 2
+#define PCRF_AZ_RX_NOT_DET_WIDTH 1
+#define PCRF_AZ_FORCE_LOS_VAL_LBN 1
+#define PCRF_AZ_FORCE_LOS_VAL_WIDTH 1
+#define PCRF_AZ_FORCE_LOS_EN_LBN 0
+#define PCRF_AZ_FORCE_LOS_EN_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AB_VPD_ADDR_REG(16bit):
+ * VPD address register
+ */
+#define PCR_AB_VPD_ADDR_REG 0x000000b2
+/* falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AB_VPD_FLAG_LBN 15
+#define PCRF_AB_VPD_FLAG_WIDTH 1
+#define PCRF_AB_VPD_ADDR_LBN 0
+#define PCRF_AB_VPD_ADDR_WIDTH 15
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AB_SYM_TMR_REG(16bit):
+ * Symbol timer register
+ */
+#define PCR_AB_SYM_TMR_REG 0x0000071c
+/* falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AB_ET_LBN 11
+#define PCRF_AB_ET_WIDTH 4
+#define PCRF_AB_SI1_LBN 8
+#define PCRF_AB_SI1_WIDTH 3
+#define PCRF_AB_SI0_LBN 0
+#define PCRF_AB_SI0_WIDTH 8
+
+
+#endif /* PCI_PROGMODEL_DEFS_H */
diff -r 0b5ca7cdbdfc -r b8c2a9aacba6
drivers/net/sfc/sfc_resource/ci/driver/efab/hardware/workarounds.h
--- a/drivers/net/sfc/sfc_resource/ci/driver/efab/hardware/workarounds.h
Fri Jan 08 13:05:49 2010 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,75 +0,0 @@
-/****************************************************************************
- * Driver for Solarflare network controllers -
- * resource management for Xen backend, OpenOnload, etc
- * (including support for SFE4001 10GBT NIC)
- *
- * This file provides workaround settings for EtherFabric NICs.
- *
- * Copyright 2005-2007: Solarflare Communications Inc,
- * 9501 Jeronimo Road, Suite 250,
- * Irvine, CA 92618, USA
- *
- * Developed and maintained by Solarflare Communications:
- * <linux-xen-drivers@xxxxxxxxxxxxxx>
- * <onload-dev@xxxxxxxxxxxxxx>
- *
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation, incorporated herein by reference.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- ****************************************************************************
- */
-
-#ifndef __CI_DRIVER_EFAB_WORKAROUNDS_H__
-#define __CI_DRIVER_EFAB_WORKAROUNDS_H__
-
-/*----------------------------------------------------------------------------
- *
- * Hardware workarounds which have global scope
- *
- *---------------------------------------------------------------------------*/
-
-#if defined(__CI_HARDWARE_CONFIG_FALCON__)
-
-#if defined(__CI_HARDWARE_CONFIG_FALCON_B0__)
-/*------------------------------- B0 ---------------------------------------*/
-
-#define BUG2175_WORKAROUND 0 /* TX event batching for dual port operation.
- This removes the effect (dup TX events)
- of the fix
- (TX event per packet + batch events) */
-#define BUG5302_WORKAROUND 0 /* unstick TX DMAQ after out-of-range wr ptr */
-#define BUG5475_WORKAROUND 1 /* 10G SNAP encapsulation broken */
-#define BUG5762_WORKAROUND 0 /* Set all queues to jumbo mode */
-#define BUG5391_WORKAROUND 0 /* Misaligned TX can't span 512-byte boundary */
-#define BUG7916_WORKAROUND 0 /* RX flush gets lost */
-
-#else
-/*------------------------------- A0/A1 ------------------------------------*/
-
-#define BUG2175_WORKAROUND 1 /* TX event batching for dual port operation.
- This removes the effect (dup TX events)
- of the fix
- (TX event per packet + batch events) */
-#define BUG5302_WORKAROUND 1 /* unstick TX DMAQ after out-of-range wr ptr */
-#define BUG5475_WORKAROUND 1 /* 10G SNAP encapsulation broken */
-#define BUG5762_WORKAROUND 1 /* Set all queues to jumbo mode */
-#define BUG5391_WORKAROUND 1 /* Misaligned TX can't span 512-byte boundary */
-#define BUG7916_WORKAROUND 1 /* RX flush gets lost */
-
-#endif /* B0/A01 */
-
-#else
-# error Need hw support.
-#endif
-
-#endif /* __CI_DRIVER_EFAB_WORKAROUNDS_H__ */
diff -r 0b5ca7cdbdfc -r b8c2a9aacba6
drivers/net/sfc/sfc_resource/ci/driver/resource/efx_vi.h
--- a/drivers/net/sfc/sfc_resource/ci/driver/resource/efx_vi.h Fri Jan 08
13:05:49 2010 +0000
+++ b/drivers/net/sfc/sfc_resource/ci/driver/resource/efx_vi.h Fri Jan 08
13:06:22 2010 +0000
@@ -5,7 +5,7 @@
*
* This file contains public EFX VI API to Solarflare resource manager.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
@@ -49,11 +49,11 @@ struct efx_vi_state;
* Allocate an efx_vi, including event queue and pt_endpoint
*
* \param vih_out Pointer to a handle that is set on success
- * \param nic_index Index of NIC to apply this resource to
+ * \param ifindex Index of the network interface desired
* \return Zero on success (and vih_out set), non-zero on failure.
*/
extern int
-efx_vi_alloc(struct efx_vi_state **vih_out, int nic_index);
+efx_vi_alloc(struct efx_vi_state **vih_out, int ifindex);
/*!
* Free a previously allocated efx_vi
diff -r 0b5ca7cdbdfc -r b8c2a9aacba6
drivers/net/sfc/sfc_resource/ci/driver/resource/linux_efhw_nic.h
--- a/drivers/net/sfc/sfc_resource/ci/driver/resource/linux_efhw_nic.h Fri Jan
08 13:05:49 2010 +0000
+++ b/drivers/net/sfc/sfc_resource/ci/driver/resource/linux_efhw_nic.h Fri Jan
08 13:06:22 2010 +0000
@@ -5,7 +5,7 @@
*
* This file contains definition of the public type struct linux_efhw_nic.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
@@ -38,8 +38,14 @@
#ifndef __CI_DRIVER_RESOURCE_LINUX_RESOURCE__
#define __CI_DRIVER_RESOURCE_LINUX_RESOURCE__
+#ifndef __linux__
+# error Silly
+#endif
+#ifndef __KERNEL__
+# error Silly
+#endif
-#include <ci/efhw/efhw_types.h>
+#include <ci/efrm/efrm_nic.h>
#include <linux/interrupt.h>
@@ -48,7 +54,7 @@
************************************************************************/
struct linux_efhw_nic {
- struct efhw_nic nic;
+ struct efrm_nic efrm_nic;
struct pci_dev *pci_dev; /*!< pci descriptor */
struct tasklet_struct tasklet; /*!< for interrupt bottom half */
@@ -64,7 +70,7 @@ struct linux_efhw_nic {
};
-#define linux_efhw_nic(efhw_nic) \
- container_of(efhw_nic, struct linux_efhw_nic, nic)
+#define linux_efhw_nic(_efhw_nic) \
+ container_of(_efhw_nic, struct linux_efhw_nic, efrm_nic.efhw_nic)
#endif /* __CI_DRIVER_RESOURCE_LINUX_RESOURCE__ */
diff -r 0b5ca7cdbdfc -r b8c2a9aacba6
drivers/net/sfc/sfc_resource/ci/efhw/checks.h
--- a/drivers/net/sfc/sfc_resource/ci/efhw/checks.h Fri Jan 08 13:05:49
2010 +0000
+++ b/drivers/net/sfc/sfc_resource/ci/efhw/checks.h Fri Jan 08 13:06:22
2010 +0000
@@ -6,7 +6,7 @@
* This file provides helpers to turn bit shifts into dword shifts and
* check that the bit fields haven't overflown the dword etc.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
@@ -49,70 +49,63 @@
#define __FALCON_MASKFIELD32(LBN, WIDTH) \
((uint32_t)(__FALCON_MASK32(WIDTH) << (LBN)))
-/* constructors for fields which span the first and second dwords */
-#define __LW(LBN) (32 - LBN)
-#define __LOW(v, LBN, WIDTH) \
- ((uint32_t)(((v) & __FALCON_MASK64(__LW((LBN)))) << (LBN)))
-#define __HIGH(v, LBN, WIDTH) \
- ((uint32_t)(((v) >> __LW((LBN))) & \
- __FALCON_MASK64((WIDTH - __LW((LBN))))))
-/* constructors for fields within the second dword */
+
+/* constructors for fields within one DWORD */
#define __DW2(LBN) ((LBN) - 32)
-
-/* constructors for fields which span the second and third dwords */
-#define __LW2(LBN) (64 - LBN)
-#define __LOW2(v, LBN, WIDTH) \
- ((uint32_t)(((v) & __FALCON_MASK64(__LW2((LBN)))) << ((LBN) - 32)))
-#define __HIGH2(v, LBN, WIDTH) \
- ((uint32_t)(((v) >> __LW2((LBN))) & \
- __FALCON_MASK64((WIDTH - __LW2((LBN))))))
-
-/* constructors for fields within the third dword */
#define __DW3(LBN) ((LBN) - 64)
-
-/* constructors for fields which span the third and fourth dwords */
-#define __LW3(LBN) (96 - LBN)
-#define __LOW3(v, LBN, WIDTH) \
- ((uint32_t)(((v) & __FALCON_MASK64(__LW3((LBN)))) << ((LBN) - 64)))
-#define __HIGH3(v, LBN, WIDTH) \
- ((ci_unit32)(((v) >> __LW3((LBN))) & \
- __FALCON_MASK64((WIDTH - __LW3((LBN))))))
-
-/* constructors for fields within the fourth dword */
#define __DW4(LBN) ((LBN) - 96)
+
+/* width for lower portion of field spanning DWORDs */
+#define __LW(LBN) (32 - LBN) /* 0 -> 1 */
+#define __LW2(LBN) (64 - LBN) /* 1 -> 2 */
+#define __LW3(LBN) (96 - LBN) /* 2 -> 3 */
+
+
+/* constructors for lower portion of field spanning DWORDs */
+#define __LOW(v, F) \
+ ((uint32_t)(((v) & __FALCON_MASK64(__LW(F##_LBN))) << (F##_LBN)))
+#define __LOW2(v, F) \
+ ((uint32_t)(((v) & __FALCON_MASK64(__LW2(F##_LBN))) << __DW2(F##_LBN)))
+#define __LOW3(v, F) \
+ ((uint32_t)(((v) & __FALCON_MASK64(__LW3(F##_LBN))) << __DW3(F##_LBN)))
+
+/* constructors for upper portion of field spanning DWORDs */
+#define __HIGH(v, F) \
+ ((uint32_t)(((v) >> __LW(F##_LBN)) & \
+ __FALCON_MASK64((F##_WIDTH - __LW(F##_LBN)))))
+#define __HIGH2(v, F) \
+ ((uint32_t)(((v) >> __LW2((F##_LBN))) & \
+ __FALCON_MASK64((F##_WIDTH - __LW2((F##_LBN))))))
+#define __HIGH3(v, F) \
+ ((unit32_t)(((v) >> __LW3((F##_LBN))) & \
+ __FALCON_MASK64((F##_WIDTH - __LW3((F##_LBN))))))
+
+
/* checks that the autogenerated headers are consistent with our model */
-#define __WIDTHCHCK(a, b) EFHW_ASSERT((a) == (b))
#define __RANGECHCK(v, WIDTH) \
EFHW_ASSERT(((uint64_t)(v) & ~(__FALCON_MASK64((WIDTH)))) == 0)
-/* fields within the first dword */
-#define __DWCHCK(LBN, WIDTH) \
- EFHW_ASSERT(((LBN) >= 0) && (((LBN)+(WIDTH)) <= 32))
-/* fields which span the first and second dwords */
-#define __LWCHK(LBN, WIDTH) EFHW_ASSERT(WIDTH >= __LW(LBN))
+/* check field width if field within a DWORD */
+#define __DWCHCK(F) \
+ EFHW_BUILD_ASSERT(((F##_LBN) >= 0) && (((F##_LBN)+(F##_WIDTH)) <= 32))
+#define __DW2CHCK(F) \
+ EFHW_BUILD_ASSERT(((F##_LBN) >= 32) && (((F##_LBN)+(F##_WIDTH)) <= 64))
+#define __DW3CHCK(F) \
+ EFHW_BUILD_ASSERT(((F##_LBN) >= 64) && (((F##_LBN)+(F##_WIDTH)) <= 96))
+#define __DW4CHCK(F) \
+ EFHW_BUILD_ASSERT(((F##_LBN) >= 96) && (((F##_LBN)+(F##_WIDTH)) <= 128))
-/* fields within the second dword */
-#define __DW2CHCK(LBN, WIDTH) \
- EFHW_ASSERT(((LBN) >= 32) && (((LBN)+(WIDTH)) <= 64))
-/* fields which span the second and third dwords */
-#define __LW2CHK(LBN, WIDTH) EFHW_ASSERT(WIDTH >= __LW2(LBN))
+/* check field width if field spans a DWORD */
+#define __LWCHK(F) EFHW_BUILD_ASSERT(F##_WIDTH >= __LW(F##_LBN))
+#define __LW2CHK(F) EFHW_BUILD_ASSERT(F##_WIDTH >= __LW2(F##_LBN))
+#define __LW3CHK(F) EFHW_BUILD_ASSERT(F##_WIDTH >= __LW3(F##_LBN))
-/* fields within the third dword */
-#define __DW3CHCK(LBN, WIDTH) \
- EFHW_ASSERT(((LBN) >= 64) && (((LBN)+(WIDTH)) <= 96))
-
-/* fields which span the third and fourth dwords */
-#define __LW3CHK(LBN, WIDTH) EFHW_ASSERT(WIDTH >= __LW3(LBN))
-
-/* fields within the fourth dword */
-#define __DW4CHCK(LBN, WIDTH) \
- EFHW_ASSERT(((LBN) >= 96) && (((LBN)+(WIDTH)) <= 128))
/* fields in the first qword */
-#define __QWCHCK(LBN, WIDTH) \
- EFHW_ASSERT(((LBN) >= 0) && (((LBN)+(WIDTH)) <= 64))
+#define __QWCHCK(F) \
+ EFHW_BUILD_ASSERT(((F##_LBN) >= 0) && (((F##_LBN)+(F##_WIDTH)) <= 64))
#endif /* __CI_EFHW_CHECK_H__ */
diff -r 0b5ca7cdbdfc -r b8c2a9aacba6
drivers/net/sfc/sfc_resource/ci/efhw/common.h
--- a/drivers/net/sfc/sfc_resource/ci/efhw/common.h Fri Jan 08 13:05:49
2010 +0000
+++ b/drivers/net/sfc/sfc_resource/ci/efhw/common.h Fri Jan 08 13:06:22
2010 +0000
@@ -6,7 +6,7 @@
* This file provides API of the efhw library which may be used both from
* the kernel and from the user-space code.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
@@ -43,7 +43,6 @@
enum efhw_arch {
EFHW_ARCH_FALCON,
- EFHW_ARCH_SIENA,
};
typedef uint32_t efhw_buffer_addr_t;
@@ -59,18 +58,24 @@ typedef union {
} efhw_event_t;
/* Flags for TX/RX queues */
-#define EFHW_VI_JUMBO_EN 0x01 /*! scatter RX over multiple desc */
-#define EFHW_VI_ISCSI_RX_HDIG_EN 0x02 /*! iscsi rx header digest */
-#define EFHW_VI_ISCSI_TX_HDIG_EN 0x04 /*! iscsi tx header digest */
-#define EFHW_VI_ISCSI_RX_DDIG_EN 0x08 /*! iscsi rx data digest */
-#define EFHW_VI_ISCSI_TX_DDIG_EN 0x10 /*! iscsi tx data digest */
-#define EFHW_VI_TX_PHYS_ADDR_EN 0x20 /*! TX physical address mode */
-#define EFHW_VI_RX_PHYS_ADDR_EN 0x40 /*! RX physical address mode */
-#define EFHW_VI_RM_WITH_INTERRUPT 0x80 /*! VI with an interrupt */
-#define EFHW_VI_TX_IP_CSUM_DIS 0x100 /*! enable ip checksum generation */
-#define EFHW_VI_TX_TCPUDP_CSUM_DIS 0x200 /*! enable tcp/udp checksum
- generation */
-#define EFHW_VI_TX_TCPUDP_ONLY 0x400 /*! drop non-tcp/udp packets */
+#define EFHW_VI_JUMBO_EN 0x01 /*! scatter RX over multiple desc */
+#define EFHW_VI_ISCSI_RX_HDIG_EN 0x02 /*! iscsi rx header digest */
+#define EFHW_VI_ISCSI_TX_HDIG_EN 0x04 /*! iscsi tx header digest */
+#define EFHW_VI_ISCSI_RX_DDIG_EN 0x08 /*! iscsi rx data digest */
+#define EFHW_VI_ISCSI_TX_DDIG_EN 0x10 /*! iscsi tx data digest */
+#define EFHW_VI_TX_PHYS_ADDR_EN 0x20 /*! TX physical address mode */
+#define EFHW_VI_RX_PHYS_ADDR_EN 0x40 /*! RX physical address mode */
+#define EFHW_VI_RM_WITH_INTERRUPT 0x80 /*! VI with an interrupt */
+#define EFHW_VI_TX_IP_CSUM_DIS 0x100 /*! enable ip checksum generation */
+#define EFHW_VI_TX_TCPUDP_CSUM_DIS 0x200 /*! enable tcp/udp checksum
+ generation */
+#define EFHW_VI_TX_TCPUDP_ONLY 0x400 /*! drop non-tcp/udp packets */
+/* from here on, Siena only: */
+#define EFHW_VI_TX_IP_FILTER_EN 0x800 /*! TX IP filtering */
+#define EFHW_VI_TX_ETH_FILTER_EN 0x1000 /*! TX MAC filtering */
+#define EFHW_VI_TX_Q_MASK_WIDTH_0 0x2000 /*! TX filter q_mask_width bit 0 */
+#define EFHW_VI_TX_Q_MASK_WIDTH_1 0x4000 /*! TX filter q_mask_width bit 1 */
+#define EFHW_VI_RX_HDR_SPLIT 0x8000 /*! RX header split */
/* Types of hardware filter */
/* Each of these values implicitly selects scatter filters on B0 - or in
@@ -95,4 +100,22 @@ typedef union {
#define EFHW_IP_FILTER_BROADCAST (0x10000) /* driverlink filter
support */
+/* Similar for RX MAC filters -- Siena only */
+#define EFHW_MAC_FILTER_TYPE_WILDCARD (0)
+#define EFHW_MAC_FILTER_TYPE_FULL (1)
+#define EFHW_MAC_FILTER_TYPE_IPOVER_WILDCARD (2)
+#define EFHW_MAC_FILTER_TYPE_IPOVER_FULL (3)
+/* Same again, but with RSS */
+#define EFHW_MAC_FILTER_TYPE_WILDCARD_RSS (4)
+#define EFHW_MAC_FILTER_TYPE_FULL_RSS (5)
+#define EFHW_MAC_FILTER_TYPE_IPOVER_WILDCARD_RSS (6)
+#define EFHW_MAC_FILTER_TYPE_IPOVER_FULL_RSS (7)
+
+#define EFHW_MAC_FILTER_TYPE_FULL_MASK (0x1) /* Mask for full / wildcard */
+#define EFHW_MAC_FILTER_TYPE_IPOVER_MASK (0x2) /* Mask for IP override flg */
+#define EFHW_MAC_FILTER_TYPE_RSS_MASK (0x4) /* Mask for RSS enable */
+#define EFHW_MAC_FILTER_TYPE_NOSCAT_MASK (0x8) /* Mask for SCATTER dsbl */
+
+#define EFHW_MAC_FILTER_TYPE_MASK (0xffff) /* Mask of types above */
+
#endif /* __CI_EFHW_COMMON_H__ */
diff -r 0b5ca7cdbdfc -r b8c2a9aacba6
drivers/net/sfc/sfc_resource/ci/efhw/common_sysdep.h
--- a/drivers/net/sfc/sfc_resource/ci/efhw/common_sysdep.h Fri Jan 08
13:05:49 2010 +0000
+++ b/drivers/net/sfc/sfc_resource/ci/efhw/common_sysdep.h Fri Jan 08
13:06:22 2010 +0000
@@ -7,7 +7,7 @@
* userland-to-kernel interfaces.
* Only kernels >=2.6.9 are supported.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
@@ -52,20 +52,12 @@
/* Linux kernel also does not provide PRIx32... Sigh. */
#define PRIx32 "x"
-
+
#ifdef __ia64__
# define PRIx64 "lx"
#else
# define PRIx64 "llx"
#endif
-#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)
-enum {
- false = 0,
- true = 1
-};
-
-typedef _Bool bool;
-#endif /* LINUX_VERSION_CODE < 2.6.19 */
#endif /* __CI_EFHW_COMMON_LINUX_H__ */
diff -r 0b5ca7cdbdfc -r b8c2a9aacba6
drivers/net/sfc/sfc_resource/ci/efhw/debug.h
--- a/drivers/net/sfc/sfc_resource/ci/efhw/debug.h Fri Jan 08 13:05:49
2010 +0000
+++ b/drivers/net/sfc/sfc_resource/ci/efhw/debug.h Fri Jan 08 13:06:22
2010 +0000
@@ -6,7 +6,7 @@
* This file provides debug-related API for efhw library using Linux kernel
* primitives.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
@@ -41,8 +41,12 @@
#define EFHW_PRINTK_PREFIX "[sfc efhw] "
+#ifndef printk_nl
+#define printk_nl "\n"
+#endif
+
#define EFHW_PRINTK(level, fmt, ...) \
- printk(level EFHW_PRINTK_PREFIX fmt "\n", __VA_ARGS__)
+ printk(level EFHW_PRINTK_PREFIX fmt printk_nl, __VA_ARGS__)
/* Following macros should be used with non-zero format parameters
* due to __VA_ARGS__ limitations. Use "%s" with __FUNCTION__ if you can't
@@ -78,7 +82,7 @@
#define __EFHW_BUILD_ASSERT_NAME(_x) __EFHW_BUILD_ASSERT_ILOATHECPP(_x)
#define __EFHW_BUILD_ASSERT_ILOATHECPP(_x) __EFHW_BUILD_ASSERT__ ##_x
#define EFHW_BUILD_ASSERT(e) \
- typedef char __EFHW_BUILD_ASSERT_NAME(__LINE__)[(e) ? 1 : -1]
+ { typedef char __EFHW_BUILD_ASSERT_NAME(__LINE__)[(e) ? 1 : -1]; }
#endif
#endif /* __CI_EFHW_DEBUG_LINUX_H__ */
diff -r 0b5ca7cdbdfc -r b8c2a9aacba6
drivers/net/sfc/sfc_resource/ci/efhw/efhw_config.h
--- a/drivers/net/sfc/sfc_resource/ci/efhw/efhw_config.h Fri Jan 08
13:05:49 2010 +0000
+++ b/drivers/net/sfc/sfc_resource/ci/efhw/efhw_config.h Fri Jan 08
13:06:22 2010 +0000
@@ -5,7 +5,7 @@
*
* This file provides some limits used in both kernel and userland code.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
diff -r 0b5ca7cdbdfc -r b8c2a9aacba6
drivers/net/sfc/sfc_resource/ci/efhw/efhw_types.h
--- a/drivers/net/sfc/sfc_resource/ci/efhw/efhw_types.h Fri Jan 08 13:05:49
2010 +0000
+++ b/drivers/net/sfc/sfc_resource/ci/efhw/efhw_types.h Fri Jan 08 13:06:22
2010 +0000
@@ -5,7 +5,7 @@
*
* This file provides struct efhw_nic and some related types.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
@@ -65,7 +65,6 @@ struct eventq_resource_hardware {
struct eventq_resource_hardware {
/*!iobuffer allocated for eventq - can be larger than eventq */
struct efhw_iopages iobuff;
- unsigned iobuff_off;
struct efhw_buffer_table_allocation buf_tbl_alloc;
int capacity; /*!< capacity of event queue */
};
@@ -86,6 +85,73 @@ struct efhw_keventq {
struct efhw_ev_handler *ev_handlers;
};
+/*--------------------------------------------------------------------
+ *
+ * filters
+ *
+ *--------------------------------------------------------------------*/
+
+enum efhw_filter_type {
+ EFHW_FILTER_TYPE_IP = 0, /* always supported */
+ EFHW_FILTER_TYPE_MAC, /* supported by Siena only */
+ EFHW_FILTER_TYPE_TX_IP, /* supported by Siena only */
+ EFHW_FILTER_TYPE_TX_MAC, /* supported by Siena only */
+ EFHW_FILTER_TYPES_NUM
+};
+
+struct efhw_filter_spec {
+ enum efhw_filter_type type;
+ uint dmaq_id;
+ union {
+ struct {
+ uint32_t saddr_le32;
+ uint32_t daddr_le32;
+ uint16_t sport_le16;
+ uint16_t dport_le16;
+ unsigned tcp : 1;
+ unsigned full : 1;
+ unsigned rss : 1; /* not supported on A1 */
+ unsigned scatter : 1; /* not supported on A1 */
+ } ip;
+ struct {
+ uint32_t saddr_le32;
+ uint32_t daddr_le32;
+ uint16_t sport_le16;
+ uint16_t dport_le16;
+ unsigned tcp : 1;
+ unsigned full : 1;
+ } tx_ip;
+ struct {
+ uint8_t mac[6];
+ uint16_t vlan_tag;
+ unsigned full : 1;
+ unsigned ip_override : 1;
+ unsigned rss : 1;
+ unsigned scatter : 1;
+ } mac;
+ struct {
+ uint8_t mac[6];
+ uint16_t vlan_tag;
+ unsigned full : 1;
+ } tx_mac;
+ } u;
+};
+
+struct efhw_filter_depth {
+ unsigned needed;
+ unsigned max;
+};
+
+struct efhw_filter_search_limits {
+ unsigned tcp_full;
+ unsigned tcp_wild;
+ unsigned udp_full;
+ unsigned udp_wild;
+ unsigned mac_full;
+ unsigned mac_wild;
+};
+
+
/**********************************************************************
* Portable HW interface. ***************************************
**********************************************************************/
@@ -131,7 +197,7 @@ struct efhw_func_ops {
/*! Set interrupt moderation strategy for the given IRQ unit
** val is in usec
*/
- void (*set_interrupt_moderation)(struct efhw_nic *nic,
+ void (*set_interrupt_moderation)(struct efhw_nic *nic, int evq,
uint val);
/*-------------- Event support ------------ */
@@ -144,20 +210,21 @@ struct efhw_func_ops {
void (*event_queue_enable) (struct efhw_nic *nic,
uint evq, /* evnt queue index */
uint evq_size, /* units of #entries */
- dma_addr_t q_base_addr, uint buf_base_id);
+ uint buf_base_id,
+ int interrupting,
+ int enable_dos_p);
/*! Disable the given event queue (and any associated timer) */
void (*event_queue_disable) (struct efhw_nic *nic, uint evq,
int timer_only);
/*! request wakeup from the NIC on a given event Q */
- void (*wakeup_request) (struct efhw_nic *nic, dma_addr_t q_base_addr,
- int next_i, int evq);
+ void (*wakeup_request) (struct efhw_nic *nic, int rd_ptr, int evq);
/*! Push a SW event on a given eventQ */
void (*sw_event) (struct efhw_nic *nic, int data, int evq);
- /*-------------- Filter support ------------ */
+ /*-------------- IP Filter API ------------ */
/*! Setup a given filter - The software can request a filter_i,
* but some EtherFabric implementations will override with
@@ -168,15 +235,12 @@ struct efhw_func_ops {
unsigned saddr_be32, unsigned sport_be16,
unsigned daddr_be32, unsigned dport_be16);
- /*! Attach a given filter to a DMAQ */
- void (*ipfilter_attach) (struct efhw_nic *nic, int filter_idx,
- int dmaq_idx);
-
- /*! Detach a filter from its DMAQ */
- void (*ipfilter_detach) (struct efhw_nic *nic, int filter_idx);
-
/*! Clear down a given filter */
void (*ipfilter_clear) (struct efhw_nic *nic, int filter_idx);
+
+ /*! Redirect given filter to a different RX DMAQ */
+ void (*ipfilter_redirect) (struct efhw_nic *nic, int filter_i,
+ int rxq_i);
/*-------------- DMA support ------------ */
@@ -223,6 +287,15 @@ struct efhw_func_ops {
/*! Commit a buffer table update */
void (*buffer_table_commit) (struct efhw_nic *nic);
+ /*-------------- New filter API ------------ */
+
+ /*! Set a given filter */
+ int (*filter_set) (struct efhw_nic *nic, struct efhw_filter_spec *spec,
+ int *filter_idx_out);
+
+ /*! Clear a given filter */
+ void (*filter_clear) (struct efhw_nic *nic, enum efhw_filter_type type,
+ int filter_idx);
};
@@ -236,6 +309,8 @@ struct efhw_device_type {
int arch; /* enum efhw_arch */
char variant; /* 'A', 'B', ... */
int revision; /* 0, 1, ... */
+ int in_fpga:1;
+ int in_cosim:1;
};
@@ -287,9 +362,6 @@ struct efhw_nic {
/*! EtherFabric Functional Units -- functions */
const struct efhw_func_ops *efhw_func;
- /* Value read from FPGA version register. Zero for asic. */
- unsigned fpga_version;
-
/*! This lock protects a number of misc NIC resources. It should
* only be used for things that can be at the bottom of the lock
* order. ie. You mustn't attempt to grab any other lock while
@@ -314,24 +386,57 @@ struct efhw_nic {
struct efhw_keventq non_interrupting_evq;
- struct efhw_iopage irq_iobuff; /*!< Falcon SYSERR interrupt */
-
- /* The new driverlink infrastructure. */
- struct efx_dl_device *net_driver_dev;
- struct efx_dlfilt_cb_s *dlfilter_cb;
-
/*! Bit masks of the sizes of event queues and dma queues supported
* by the nic. */
unsigned evq_sizes;
unsigned rxq_sizes;
unsigned txq_sizes;
- /* Size of filter table (including odd and even banks). */
- unsigned filter_tbl_size;
+ /* Size of filter tables. */
+ unsigned ip_filter_tbl_size;
+ unsigned mac_filter_tbl_size;
+ unsigned tx_ip_filter_tbl_size;
+ unsigned tx_mac_filter_tbl_size;
+
+ /* Number of filters currently used in each filter table */
+ unsigned ip_filter_tbl_used;
+ unsigned mac_filter_tbl_used;
+ unsigned tx_ip_filter_tbl_used;
+ unsigned tx_mac_filter_tbl_used;
+
+ /* Dynamically allocated filter state. */
+ uint8_t *filter_in_use;
+ struct efhw_filter_spec *filter_spec_cache;
+
+ /* Currently required and maximum filter table search depths. */
+ struct efhw_filter_depth tcp_full_srch;
+ struct efhw_filter_depth tcp_wild_srch;
+ struct efhw_filter_depth udp_full_srch;
+ struct efhw_filter_depth udp_wild_srch;
+ struct efhw_filter_depth mac_full_srch;
+ struct efhw_filter_depth mac_wild_srch;
+ struct efhw_filter_depth tx_tcp_full_srch;
+ struct efhw_filter_depth tx_tcp_wild_srch;
+ struct efhw_filter_depth tx_udp_full_srch;
+ struct efhw_filter_depth tx_udp_wild_srch;
+ struct efhw_filter_depth tx_mac_full_srch;
+ struct efhw_filter_depth tx_mac_wild_srch;
+
+ /* Number of event queues, DMA queues and timers. */
+ unsigned num_evqs;
+ unsigned num_dmaqs;
+ unsigned num_timers;
};
#define EFHW_KVA(nic) ((nic)->bar_ioaddr)
+static inline int efhw_in_fpga(struct efhw_nic *nic) {
+ return nic->devtype.in_fpga;
+}
+
+static inline int efhw_in_cosim(struct efhw_nic *nic) {
+ return nic->devtype.in_cosim;
+}
#endif /* __CI_EFHW_EFHW_TYPES_H__ */
diff -r 0b5ca7cdbdfc -r b8c2a9aacba6
drivers/net/sfc/sfc_resource/ci/efhw/eventq.h
--- a/drivers/net/sfc/sfc_resource/ci/efhw/eventq.h Fri Jan 08 13:05:49
2010 +0000
+++ b/drivers/net/sfc/sfc_resource/ci/efhw/eventq.h Fri Jan 08 13:06:22
2010 +0000
@@ -6,7 +6,7 @@
* This file contains API provided by efhw/eventq.c file. This file is not
* designed for use outside of the SFC resource driver.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
@@ -49,7 +49,7 @@ struct efhw_ev_handler {
struct efhw_ev_handler {
void (*wakeup_fn)(struct efhw_nic *nic, unsigned);
void (*timeout_fn)(struct efhw_nic *nic, unsigned);
- void (*dmaq_flushed_fn) (struct efhw_nic *, unsigned, int);
+ void (*dmaq_flushed_fn) (struct efhw_nic *, unsigned, int, int);
};
extern int efhw_keventq_ctor(struct efhw_nic *, int instance,
diff -r 0b5ca7cdbdfc -r b8c2a9aacba6
drivers/net/sfc/sfc_resource/ci/efhw/eventq_macros.h
--- a/drivers/net/sfc/sfc_resource/ci/efhw/eventq_macros.h Fri Jan 08
13:05:49 2010 +0000
+++ b/drivers/net/sfc/sfc_resource/ci/efhw/eventq_macros.h Fri Jan 08
13:06:22 2010 +0000
@@ -6,7 +6,7 @@
* This file provides some event-related macros. This file is designed for
* use from kernel and from the userland contexts.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
@@ -60,20 +60,16 @@
#define EFHW_EVENTQ_PREV(s) \
do { ((s)->evq_ptr -= sizeof(efhw_event_t)); } while (0)
-/* Be worried about this on byteswapped machines */
-#if defined(__CI_HARDWARE_CONFIG_FALCON__)
/* Due to crazy chipsets, we see the event words being written in
- ** arbitrary order (bug4539). So test for presence of event must ensure
- ** that both halves have changed from the null.
+ * arbitrary order (bug4539). So test for presence of event must ensure
+ * that both halves have changed from the null.
*/
#define EFHW_IS_EVENT(evp) \
(((evp)->opaque.a != (uint32_t)-1) && \
((evp)->opaque.b != (uint32_t)-1))
#define EFHW_CLEAR_EVENT(evp) ((evp)->u64 = (uint64_t)-1)
#define EFHW_CLEAR_EVENT_VALUE 0xff
-#else
- #error Fixme - unknown hardware configuration
-#endif
+
#define EFHW_EVENT_OVERFLOW(evq, s) \
(EFHW_IS_EVENT(EFHW_EVENT_PTR(evq, s, 1)))
diff -r 0b5ca7cdbdfc -r b8c2a9aacba6
drivers/net/sfc/sfc_resource/ci/efhw/falcon.h
--- a/drivers/net/sfc/sfc_resource/ci/efhw/falcon.h Fri Jan 08 13:05:49
2010 +0000
+++ b/drivers/net/sfc/sfc_resource/ci/efhw/falcon.h Fri Jan 08 13:06:22
2010 +0000
@@ -6,7 +6,7 @@
* This file contains API provided by efhw/falcon.c file. This file is not
* designed for use outside of the SFC resource driver.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
@@ -59,6 +59,13 @@ extern struct efhw_func_ops falcon_char_
/*! specify a pace value for a TX DMA Queue */
extern void falcon_nic_pace(struct efhw_nic *nic, uint dmaq, uint pace);
+/*! configure the pace engine */
+extern void falcon_nic_pace_cfg(struct efhw_nic *nic, int fb_base,
+ int bin_thresh);
+
+/*! Set wakeup mask. Falcon B0 and later. */
+extern void falcon_nic_wakeup_mask_set(struct efhw_nic *nic, unsigned mask);
+
/*! confirm buffer table updates - should be used for items where
loss of data would be unacceptable. E.g for the buffers that back
an event or DMA queue */
@@ -73,16 +80,14 @@ falcon_handle_char_event(struct efhw_nic
/*! Acknowledge to HW that processing is complete on a given event queue */
extern void falcon_nic_evq_ack(struct efhw_nic *nic, uint evq, /* evq id */
- uint rptr, /* new read pointer update */
- bool wakeup /* request a wakeup event if
- ptr's != */
- );
+ uint rptr /* new read pointer update */);
extern void
falcon_nic_buffer_table_set_n(struct efhw_nic *nic, int buffer_id,
dma_addr_t dma_addr, uint bufsz, uint region,
int n_pages, int own_id);
-extern void falcon_nic_ipfilter_ctor(struct efhw_nic *nic);
+extern int falcon_nic_filter_ctor(struct efhw_nic *nic);
+
#endif /* __CI_EFHW_FALCON_H__ */
diff -r 0b5ca7cdbdfc -r b8c2a9aacba6
drivers/net/sfc/sfc_resource/ci/efhw/falcon_hash.h
--- a/drivers/net/sfc/sfc_resource/ci/efhw/falcon_hash.h Fri Jan 08
13:05:49 2010 +0000
+++ b/drivers/net/sfc/sfc_resource/ci/efhw/falcon_hash.h Fri Jan 08
13:06:22 2010 +0000
@@ -7,7 +7,7 @@
* Function declared in this file are not exported from the Linux
* sfc_resource driver.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
@@ -40,16 +40,32 @@
#ifndef __CI_EFHW_FALCON_HASH_H__
#define __CI_EFHW_FALCON_HASH_H__
-/* All LE parameters */
+/* For Falcon and Siena: IP filter table key */
extern unsigned int
-falcon_hash_get_key(unsigned int src_ip, unsigned int src_port,
- unsigned int dest_ip, unsigned int dest_port,
- int tcp, int full);
+falcon_hash_get_ip_key(unsigned int src_ip, unsigned int src_port,
+ unsigned int dest_ip, unsigned int dest_port,
+ int tcp, int full);
-unsigned int falcon_hash_function1(unsigned int key, unsigned int nfilters);
+/* For Siena only: MAC filter table key */
+extern unsigned int
+falcon_hash_get_mac_key(unsigned char *mac, unsigned int vlan, int full);
+
+/* For Siena only: TX IP filter table key */
+extern unsigned int
+falcon_hash_get_tx_ip_key(unsigned int src_ip, unsigned int src_port,
+ unsigned int dest_ip, unsigned int dest_port,
+ int tcp, int full, unsigned int masked_q_id);
+
+/* For Siena only: TX MAC filter table key */
+extern unsigned int
+falcon_hash_get_tx_mac_key(unsigned char *mac, unsigned int vlan, int full,
+ unsigned int masked_q_id);
extern unsigned int
-falcon_hash_function2(unsigned int key, unsigned int nfitlers);
+falcon_hash_function1(unsigned int key, unsigned int nfilters);
+
+extern unsigned int
+falcon_hash_function2(unsigned int key, unsigned int nfilters);
extern unsigned int
falcon_hash_iterator(unsigned int hash1, unsigned int hash2,
diff -r 0b5ca7cdbdfc -r b8c2a9aacba6
drivers/net/sfc/sfc_resource/ci/efhw/hardware_sysdep.h
--- a/drivers/net/sfc/sfc_resource/ci/efhw/hardware_sysdep.h Fri Jan 08
13:05:49 2010 +0000
+++ b/drivers/net/sfc/sfc_resource/ci/efhw/hardware_sysdep.h Fri Jan 08
13:06:22 2010 +0000
@@ -7,7 +7,7 @@
* with hardware-related definitions (in ci/driver/efab/hardware*).
* Only kernels >=2.6.9 are supported.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
@@ -40,7 +40,12 @@
#ifndef __CI_EFHW_HARDWARE_LINUX_H__
#define __CI_EFHW_HARDWARE_LINUX_H__
+#include <linux/version.h>
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,16)
+#include <linux/io.h>
+#else
#include <asm/io.h>
+#endif
#ifdef __LITTLE_ENDIAN
#define EFHW_IS_LITTLE_ENDIAN
diff -r 0b5ca7cdbdfc -r b8c2a9aacba6
drivers/net/sfc/sfc_resource/ci/efhw/iopage.h
--- a/drivers/net/sfc/sfc_resource/ci/efhw/iopage.h Fri Jan 08 13:05:49
2010 +0000
+++ b/drivers/net/sfc/sfc_resource/ci/efhw/iopage.h Fri Jan 08 13:06:22
2010 +0000
@@ -7,7 +7,7 @@
* The implementation of these functions is highly OS-dependent.
* This file is not designed for use outside of the SFC resource driver.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
diff -r 0b5ca7cdbdfc -r b8c2a9aacba6
drivers/net/sfc/sfc_resource/ci/efhw/iopage_types.h
--- a/drivers/net/sfc/sfc_resource/ci/efhw/iopage_types.h Fri Jan 08
13:05:49 2010 +0000
+++ b/drivers/net/sfc/sfc_resource/ci/efhw/iopage_types.h Fri Jan 08
13:06:22 2010 +0000
@@ -6,7 +6,7 @@
* This file provides struct efhw_page and struct efhw_iopage for Linux
* kernel.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
diff -r 0b5ca7cdbdfc -r b8c2a9aacba6 drivers/net/sfc/sfc_resource/ci/efhw/nic.h
--- a/drivers/net/sfc/sfc_resource/ci/efhw/nic.h Fri Jan 08 13:05:49
2010 +0000
+++ b/drivers/net/sfc/sfc_resource/ci/efhw/nic.h Fri Jan 08 13:06:22
2010 +0000
@@ -6,7 +6,7 @@
* This file contains API provided by efhw/nic.c file. This file is not
* designed for use outside of the SFC resource driver.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
diff -r 0b5ca7cdbdfc -r b8c2a9aacba6
drivers/net/sfc/sfc_resource/ci/efhw/public.h
--- a/drivers/net/sfc/sfc_resource/ci/efhw/public.h Fri Jan 08 13:05:49
2010 +0000
+++ b/drivers/net/sfc/sfc_resource/ci/efhw/public.h Fri Jan 08 13:06:22
2010 +0000
@@ -6,7 +6,7 @@
* This file provides public API of efhw library exported from the SFC
* resource driver.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
@@ -70,11 +70,50 @@ extern void falcon_nic_set_rx_usr_buf_si
extern void falcon_nic_set_rx_usr_buf_size(struct efhw_nic *,
int rx_usr_buf_size);
+/*! Get RX filter search limits from RX_FILTER_CTL_REG.
+ * use_raw_values = 0 to get actual depth of search, or 1 to get raw values
+ * from register.
+ */
+extern void
+falcon_nic_get_rx_filter_search_limits(struct efhw_nic *nic,
+ struct efhw_filter_search_limits *lim,
+ int use_raw_values);
+
+/*! Set RX filter search limits in RX_FILTER_CTL_REG.
+ * use_raw_values = 0 if specifying actual depth of search, or 1 if specifying
+ * raw values to write to the register.
+ */
+extern void
+falcon_nic_set_rx_filter_search_limits(struct efhw_nic *nic,
+ struct efhw_filter_search_limits *lim,
+ int use_raw_values);
+
+/*! Get TX filter search limits from TX_CFG_REG (on Siena only).
+ * use_raw_values = 0 to get actual depth of search, or 1 to get raw values
+ * from register.
+ */
+extern void
+falcon_nic_get_tx_filter_search_limits(struct efhw_nic *nic,
+ struct efhw_filter_search_limits *lim,
+ int use_raw_values);
+
+/*! Set TX filter search limits in TX_CFG_REG (on Siena only).
+ * use_raw_values = 0 if specifying actual depth of search, or 1 if specifying
+ * raw values to write to the register.
+ */
+extern void
+falcon_nic_set_tx_filter_search_limits(struct efhw_nic *nic,
+ struct efhw_filter_search_limits *lim,
+ int use_raw_values);
+
+
+/*! Legacy RX IP filter search depth control interface */
extern void
falcon_nic_rx_filter_ctl_set(struct efhw_nic *nic, uint32_t tcp_full,
uint32_t tcp_wild,
uint32_t udp_full, uint32_t udp_wild);
+/*! Legacy RX IP filter search depth control interface */
extern void
falcon_nic_rx_filter_ctl_get(struct efhw_nic *nic, uint32_t *tcp_full,
uint32_t *tcp_wild,
diff -r 0b5ca7cdbdfc -r b8c2a9aacba6
drivers/net/sfc/sfc_resource/ci/efhw/sysdep.h
--- a/drivers/net/sfc/sfc_resource/ci/efhw/sysdep.h Fri Jan 08 13:05:49
2010 +0000
+++ b/drivers/net/sfc/sfc_resource/ci/efhw/sysdep.h Fri Jan 08 13:06:22
2010 +0000
@@ -6,7 +6,7 @@
* This file provides version-independent Linux kernel API for efhw library.
* Only kernels >=2.6.9 are supported.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
@@ -43,17 +43,14 @@
#include <linux/module.h>
#include <linux/spinlock.h>
#include <linux/delay.h>
+#include <linux/vmalloc.h>
#include <linux/if_ether.h>
#include <linux/netdevice.h> /* necessary for etherdevice.h on some kernels */
#include <linux/etherdevice.h>
-#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
-static inline int is_local_ether_addr(const u8 *addr)
-{
- return (0x02 & addr[0]);
-}
-#endif
+#include "kernel_compat.h"
+
typedef unsigned long irq_flags_t;
@@ -63,10 +60,8 @@ typedef unsigned long irq_flags_t;
#define HAS_NET_NAMESPACE
#endif
-/* Funny, but linux has round_up for x86 only, defined in
- * x86-specific header */
-#ifndef round_up
-#define round_up(x, y) (((x) + (y) - 1) & ~((y)-1))
+#ifndef roundup
+#define roundup(x, y) (((x) + (y) - 1) & ~((y)-1))
#endif
#endif /* __CI_EFHW_SYSDEP_LINUX_H__ */
diff -r 0b5ca7cdbdfc -r b8c2a9aacba6
drivers/net/sfc/sfc_resource/ci/efrm/buddy.h
--- a/drivers/net/sfc/sfc_resource/ci/efrm/buddy.h Fri Jan 08 13:05:49
2010 +0000
+++ b/drivers/net/sfc/sfc_resource/ci/efrm/buddy.h Fri Jan 08 13:06:22
2010 +0000
@@ -6,7 +6,7 @@
* This file provides private API for buddy allocator. This API is not
* designed for use outside of SFC resource driver.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
@@ -63,7 +63,6 @@ int efrm_buddy_alloc(struct efrm_buddy_a
int efrm_buddy_alloc(struct efrm_buddy_allocator *b, unsigned order);
void efrm_buddy_free(struct efrm_buddy_allocator *b, unsigned addr,
unsigned order);
-void efrm_buddy_reserve_at_start(struct efrm_buddy_allocator *b, unsigned n);
-void efrm_buddy_reserve_at_end(struct efrm_buddy_allocator *b, unsigned n);
+
#endif /* __CI_EFRM_BUDDY_H__ */
diff -r 0b5ca7cdbdfc -r b8c2a9aacba6
drivers/net/sfc/sfc_resource/ci/efrm/buffer_table.h
--- a/drivers/net/sfc/sfc_resource/ci/efrm/buffer_table.h Fri Jan 08
13:05:49 2010 +0000
+++ b/drivers/net/sfc/sfc_resource/ci/efrm/buffer_table.h Fri Jan 08
13:06:22 2010 +0000
@@ -6,7 +6,7 @@
* This file provides private buffer table API. This API is not designed
* for use outside of SFC resource driver.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
@@ -60,10 +60,6 @@ extern int efrm_buffer_table_alloc(unsig
extern int efrm_buffer_table_alloc(unsigned order,
struct efhw_buffer_table_allocation *a);
-/*! current size of the buffer table.
- * FIXME This function should be inline, but it is never used from
- * the fast path, so let it as-is. */
-unsigned long efrm_buffer_table_size(void);
/*--------------------------------------------------------------------
*
@@ -75,12 +71,11 @@ extern void efrm_buffer_table_free(struc
extern void efrm_buffer_table_free(struct efhw_buffer_table_allocation *a);
/*! commit the update of a buffer table entry to every NIC */
-void efrm_buffer_table_commit(void);
+extern void efrm_buffer_table_commit(void);
-/*! set a given buffer table entry. [pa] should be the physical
- address of pinned down memory. This function can only be called from
- the char driver */
-void efrm_buffer_table_set(struct efhw_buffer_table_allocation *a,
- unsigned i, dma_addr_t dma_addr, int owner);
+extern void efrm_buffer_table_set(struct efhw_buffer_table_allocation *,
+ struct efhw_nic *,
+ unsigned i, dma_addr_t dma_addr, int owner);
+
#endif /* __CI_EFRM_BUFFER_TABLE_H__ */
diff -r 0b5ca7cdbdfc -r b8c2a9aacba6
drivers/net/sfc/sfc_resource/ci/efrm/debug.h
--- a/drivers/net/sfc/sfc_resource/ci/efrm/debug.h Fri Jan 08 13:05:49
2010 +0000
+++ b/drivers/net/sfc/sfc_resource/ci/efrm/debug.h Fri Jan 08 13:06:22
2010 +0000
@@ -6,7 +6,7 @@
* This file provides debug-related API for efrm library using Linux kernel
* primitives.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
@@ -50,7 +50,7 @@
#define EFRM_ERR(fmt, ...) EFRM_PRINTK(KERN_ERR, fmt, __VA_ARGS__)
#define EFRM_WARN(fmt, ...) EFRM_PRINTK(KERN_WARNING, fmt, __VA_ARGS__)
#define EFRM_NOTICE(fmt, ...) EFRM_PRINTK(KERN_NOTICE, fmt, __VA_ARGS__)
-#if 0 && !defined(NDEBUG)
+#if !defined(NDEBUG)
#define EFRM_TRACE(fmt, ...) EFRM_PRINTK(KERN_DEBUG, fmt, __VA_ARGS__)
#else
#define EFRM_TRACE(fmt, ...)
diff -r 0b5ca7cdbdfc -r b8c2a9aacba6
drivers/net/sfc/sfc_resource/ci/efrm/driver_private.h
--- a/drivers/net/sfc/sfc_resource/ci/efrm/driver_private.h Fri Jan 08
13:05:49 2010 +0000
+++ b/drivers/net/sfc/sfc_resource/ci/efrm/driver_private.h Fri Jan 08
13:06:22 2010 +0000
@@ -6,7 +6,7 @@
* This file provides private API of efrm library to be used from the SFC
* resource driver.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
@@ -57,10 +57,13 @@ extern struct efrm_resource_manager *efr
*
*--------------------------------------------------------------------*/
-extern int efrm_driver_ctor(void);
-extern int efrm_driver_dtor(void);
-extern int efrm_driver_register_nic(struct efhw_nic *, int nic_index);
-extern int efrm_driver_unregister_nic(struct efhw_nic *);
+struct efrm_nic;
+
+extern void efrm_driver_ctor(void);
+extern void efrm_driver_dtor(void);
+extern int efrm_driver_register_nic(struct efrm_nic *, int nic_index,
+ int ifindex);
+extern int efrm_driver_unregister_nic(struct efrm_nic *);
/*--------------------------------------------------------------------
*
diff -r 0b5ca7cdbdfc -r b8c2a9aacba6
drivers/net/sfc/sfc_resource/ci/efrm/efrm_client.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/net/sfc/sfc_resource/ci/efrm/efrm_client.h Fri Jan 08
13:06:22 2010 +0000
@@ -0,0 +1,65 @@
+/****************************************************************************
+ * Driver for Solarflare network controllers -
+ * resource management for Xen backend, OpenOnload, etc
+ * (including support for SFE4001 10GBT NIC)
+ *
+ * This file provides helpers to turn bit shifts into dword shifts and
+ * check that the bit fields haven't overflown the dword etc.
+ *
+ * Copyright 2005-2010: Solarflare Communications Inc,
+ * 9501 Jeronimo Road, Suite 250,
+ * Irvine, CA 92618, USA
+ *
+ * Developed and maintained by Solarflare Communications:
+ * <linux-xen-drivers@xxxxxxxxxxxxxx>
+ * <onload-dev@xxxxxxxxxxxxxx>
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation, incorporated herein by reference.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ ****************************************************************************
+ */
+
+#ifndef __EFRM_CLIENT_H__
+#define __EFRM_CLIENT_H__
+
+
+struct efrm_client;
+
+
+struct efrm_client_callbacks {
+ /* Called before device is reset. Callee may block. */
+ void (*pre_reset)(struct efrm_client *, void *user_data);
+ void (*stop)(struct efrm_client *, void *user_data);
+ void (*restart)(struct efrm_client *, void *user_data);
+};
+
+
+#define EFRM_IFINDEX_DEFAULT -1
+
+
+/* NB. Callbacks may be invoked even before this returns. */
+extern int efrm_client_get(int ifindex, struct efrm_client_callbacks *,
+ void *user_data, struct efrm_client **client_out);
+extern void efrm_client_put(struct efrm_client *);
+
+extern struct efhw_nic *efrm_client_get_nic(struct efrm_client *);
+extern int efrm_client_get_ifindex(struct efrm_client *);
+
+#if 0
+/* For each resource type... */
+extern void efrm_x_resource_resume(struct x_resource *);
+#endif
+
+
+#endif /* __EFRM_CLIENT_H__ */
diff -r 0b5ca7cdbdfc -r b8c2a9aacba6
drivers/net/sfc/sfc_resource/ci/efrm/efrm_nic.h
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/net/sfc/sfc_resource/ci/efrm/efrm_nic.h Fri Jan 08 13:06:22
2010 +0000
@@ -0,0 +1,58 @@
+/****************************************************************************
+ * Driver for Solarflare network controllers -
+ * resource management for Xen backend, OpenOnload, etc
+ * (including support for SFE4001 10GBT NIC)
+ *
+ * This file provides helpers to turn bit shifts into dword shifts and
+ * check that the bit fields haven't overflown the dword etc.
+ *
+ * Copyright 2005-2010: Solarflare Communications Inc,
+ * 9501 Jeronimo Road, Suite 250,
+ * Irvine, CA 92618, USA
+ *
+ * Developed and maintained by Solarflare Communications:
+ * <linux-xen-drivers@xxxxxxxxxxxxxx>
+ * <onload-dev@xxxxxxxxxxxxxx>
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation, incorporated herein by reference.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ ****************************************************************************
+ */
+
+#ifndef __EFRM_NIC_H__
+#define __EFRM_NIC_H__
+
+#include <ci/efhw/efhw_types.h>
+
+
+struct efrm_nic_per_vi {
+ unsigned long state;
+ struct vi_resource *vi;
+};
+
+
+struct efrm_nic {
+ struct efhw_nic efhw_nic;
+ struct list_head link;
+ struct list_head clients;
+ struct efrm_nic_per_vi *vis;
+};
+
+
+#define efrm_nic(_efhw_nic) \
+ container_of(_efhw_nic, struct efrm_nic, efhw_nic)
+
+
+
+#endif /* __EFRM_NIC_H__ */
diff -r 0b5ca7cdbdfc -r b8c2a9aacba6
drivers/net/sfc/sfc_resource/ci/efrm/filter.h
--- a/drivers/net/sfc/sfc_resource/ci/efrm/filter.h Fri Jan 08 13:05:49
2010 +0000
+++ b/drivers/net/sfc/sfc_resource/ci/efrm/filter.h Fri Jan 08 13:06:22
2010 +0000
@@ -5,7 +5,7 @@
*
* This file provides public API for filter resource.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
@@ -39,19 +39,14 @@
#define __CI_EFRM_FILTER_H__
#include <ci/efrm/resource.h>
-#include <ci/efrm/vi_resource.h>
-#include <ci/efrm/nic_set.h>
#include <ci/efhw/common.h>
+#include <ci/efrm/debug.h>
-/*! Comment? */
-struct filter_resource {
- struct efrm_resource rs;
- struct vi_resource *pt;
- int filter_idx;
- efrm_nic_set_t nic_set;
-};
-#define filter_resource(rs1) container_of((rs1), struct filter_resource, rs)
+struct filter_resource;
+struct vi_resource;
+struct efrm_client;
+
/*!
* Allocate filter resource.
@@ -66,82 +61,36 @@ efrm_filter_resource_alloc(struct vi_res
efrm_filter_resource_alloc(struct vi_resource *vi_parent,
struct filter_resource **frs_out);
-/* efrm_filter_resource_free should be called only if
- * __efrm_resource_ref_count_zero() returned true.
- * The easiest way is to call efrm_filter_resource_release() */
-void efrm_filter_resource_free(struct filter_resource *frs);
-static inline void efrm_filter_resource_release(struct filter_resource *frs)
-{
- unsigned id;
+extern void
+efrm_filter_resource_release(struct filter_resource *);
- EFRM_RESOURCE_ASSERT_VALID(&frs->rs, 0);
- id = EFRM_RESOURCE_INSTANCE(frs->rs.rs_handle);
-
- if (atomic_dec_and_test(&frs->rs.rs_ref_count)) {
- if (__efrm_resource_ref_count_zero(EFRM_RESOURCE_FILTER, id)) {
- EFRM_ASSERT(EFRM_RESOURCE_INSTANCE(frs->rs.rs_handle) ==
- id);
- efrm_filter_resource_free(frs);
- }
- }
-}
-
-/*--------------------------------------------------------------------
- *!
- * Called to set/change the PT endpoint of a filter
- *
- * Example of use is TCP helper when it finds a wildcard IP filter
- * needs to change which application it delivers traffic to
- *
- * \param frs filter resource
- * \param pt_handle handle of new PT endpoint
- *
- * \return standard error codes
- *
- *--------------------------------------------------------------------*/
-extern int
-efrm_filter_resource_set_ptresource(struct filter_resource *frs,
- struct vi_resource *virs);
extern int efrm_filter_resource_clear(struct filter_resource *frs);
-extern int __efrm_filter_resource_set(struct filter_resource *frs, int type,
- unsigned saddr_be32, uint16_t sport_be16,
- unsigned daddr_be32, uint16_t dport_be16);
+extern int efrm_filter_resource_ip_set(struct filter_resource *frs,
+ int protocol,
+ unsigned saddr_be32, int sport_be16,
+ unsigned daddr_be32, int dport_be16);
-static inline int
-efrm_filter_resource_tcp_set(struct filter_resource *frs,
- unsigned saddr, uint16_t sport,
- unsigned daddr, uint16_t dport)
-{
- int type;
+extern int efrm_filter_resource_set(struct filter_resource *frs, int type,
+ unsigned saddr_be32, int sport_be16,
+ unsigned daddr_be32, int dport_be16);
- EFRM_ASSERT((saddr && sport) || (!saddr && !sport));
+extern void efrm_filter_resource_redirect(struct filter_resource *frs,
+ struct vi_resource *vi);
- type =
- saddr ? EFHW_IP_FILTER_TYPE_TCP_FULL :
- EFHW_IP_FILTER_TYPE_TCP_WILDCARD;
+extern int
+efrm_filter_resource_instance(struct filter_resource *);
- return __efrm_filter_resource_set(frs, type,
- saddr, sport, daddr, dport);
-}
+extern struct efrm_resource *
+efrm_filter_resource_to_resource(struct filter_resource *);
-static inline int
-efrm_filter_resource_udp_set(struct filter_resource *frs,
- unsigned saddr, uint16_t sport,
- unsigned daddr, uint16_t dport)
-{
- int type;
+extern struct filter_resource *
+efrm_filter_resource_from_resource(struct efrm_resource *);
- EFRM_ASSERT((saddr && sport) || (!saddr && !sport));
+extern void
+efrm_filter_resource_free(struct filter_resource *);
- type =
- saddr ? EFHW_IP_FILTER_TYPE_UDP_FULL :
- EFHW_IP_FILTER_TYPE_UDP_WILDCARD;
-
- return __efrm_filter_resource_set(frs,
- type, saddr, sport, daddr, dport);
-}
#endif /* __CI_EFRM_FILTER_H__ */
/*! \cidoxg_end */
diff -r 0b5ca7cdbdfc -r b8c2a9aacba6
drivers/net/sfc/sfc_resource/ci/efrm/iobufset.h
--- a/drivers/net/sfc/sfc_resource/ci/efrm/iobufset.h Fri Jan 08 13:05:49
2010 +0000
+++ b/drivers/net/sfc/sfc_resource/ci/efrm/iobufset.h Fri Jan 08 13:06:22
2010 +0000
@@ -5,7 +5,7 @@
*
* This file provides public API for iobufset resource.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
@@ -50,11 +50,11 @@ struct iobufset_resource {
struct iobufset_resource {
struct efrm_resource rs;
struct vi_resource *evq;
+ struct iobufset_resource *linked;
struct efhw_buffer_table_allocation buf_tbl_alloc;
- unsigned int faultonaccess;
unsigned int n_bufs;
unsigned int pages_per_contiguous_chunk;
- unsigned order;
+ unsigned chunk_order;
struct efhw_iopage bufs[1];
/*!< up to n_bufs can follow this, so this must be the last member */
};
@@ -65,37 +65,24 @@ struct iobufset_resource {
/*!
* Allocate iobufset resource.
*
- * \param vi_evq VI resource to use. The function takes
- * reference to the VI resource on success.
- * \param iobrs_out pointer to return the new filter resource
+ * \param vi VI that "owns" these buffers. Grabs a reference
+ * on success.
+ * \param linked Uses memory from an existing iobufset. Grabs a
+ * reference on success.
+ * \param iobrs_out pointer to return the new filter resource
*
* \return status code; if non-zero, frs_out is unchanged
*/
extern int
efrm_iobufset_resource_alloc(int32_t n_pages,
int32_t pages_per_contiguous_chunk,
- struct vi_resource *vi_evq,
+ struct vi_resource *vi,
+ struct iobufset_resource *linked,
bool phys_addr_mode,
- uint32_t faultonaccess,
struct iobufset_resource **iobrs_out);
-/* efrm_iobufset_resource_free should be called only if
- * __efrm_resource_ref_count_zero() returned true.
- * The easiest way is to call efrm_iobufset_resource_release() */
-void efrm_iobufset_resource_free(struct iobufset_resource *rs);
-static inline void
-efrm_iobufset_resource_release(struct iobufset_resource *iobrs)
-{
- unsigned id;
-
- EFRM_RESOURCE_ASSERT_VALID(&iobrs->rs, 0);
- id = EFRM_RESOURCE_INSTANCE(iobrs->rs.rs_handle);
-
- if (atomic_dec_and_test(&iobrs->rs.rs_ref_count)) {
- if (__efrm_resource_ref_count_zero(EFRM_RESOURCE_IOBUFSET, id))
- efrm_iobufset_resource_free(iobrs);
- }
-}
+extern void efrm_iobufset_resource_free(struct iobufset_resource *);
+extern void efrm_iobufset_resource_release(struct iobufset_resource *);
static inline char *
efrm_iobufset_ptr(struct iobufset_resource *rs, unsigned offs)
diff -r 0b5ca7cdbdfc -r b8c2a9aacba6
drivers/net/sfc/sfc_resource/ci/efrm/nic_set.h
--- a/drivers/net/sfc/sfc_resource/ci/efrm/nic_set.h Fri Jan 08 13:05:49
2010 +0000
+++ b/drivers/net/sfc/sfc_resource/ci/efrm/nic_set.h Fri Jan 08 13:06:22
2010 +0000
@@ -5,7 +5,7 @@
*
* This file provides public API for NIC sets.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
diff -r 0b5ca7cdbdfc -r b8c2a9aacba6
drivers/net/sfc/sfc_resource/ci/efrm/nic_table.h
--- a/drivers/net/sfc/sfc_resource/ci/efrm/nic_table.h Fri Jan 08 13:05:49
2010 +0000
+++ b/drivers/net/sfc/sfc_resource/ci/efrm/nic_table.h Fri Jan 08 13:06:22
2010 +0000
@@ -5,7 +5,7 @@
*
* This file provides public API for NIC table.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
@@ -76,7 +76,7 @@ static inline void efrm_nic_table_rele(v
static inline int efrm_nic_table_held(void)
{
- return (atomic_read(&efrm_nic_tablep->ref_count) != 0);
+ return atomic_read(&efrm_nic_tablep->ref_count) != 0;
}
/* Run code block _x multiple times with variable nic set to each
diff -r 0b5ca7cdbdfc -r b8c2a9aacba6
drivers/net/sfc/sfc_resource/ci/efrm/private.h
--- a/drivers/net/sfc/sfc_resource/ci/efrm/private.h Fri Jan 08 13:05:49
2010 +0000
+++ b/drivers/net/sfc/sfc_resource/ci/efrm/private.h Fri Jan 08 13:06:22
2010 +0000
@@ -6,7 +6,7 @@
* This file provides private API of efrm library -- resource handling.
* This API is not designed for use outside of SFC resource driver.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
@@ -62,22 +62,6 @@ efrm_create_vi_resource_manager(struct e
efrm_create_vi_resource_manager(struct efrm_resource_manager **out,
const struct vi_resource_dimensions *);
-/*--------------------------------------------------------------------
- *
- * efrm_resource_handle_t handling
- *
- *--------------------------------------------------------------------*/
-
-/*! Initialize an area of memory to be used as a resource */
-static inline void efrm_resource_init(struct efrm_resource *rs,
- int type, int instance)
-{
- EFRM_ASSERT(instance >= 0);
- EFRM_ASSERT(type >= 0 && type < EFRM_RESOURCE_NUM);
- atomic_set(&rs->rs_ref_count, 1);
- rs->rs_handle.handle = (type << 28u) |
- (((unsigned)jiffies & 0xfff) << 16) | instance;
-}
/*--------------------------------------------------------------------
*
@@ -93,16 +77,7 @@ efrm_kfifo_id_ctor(struct kfifo **ids_ou
unsigned int i;
struct kfifo *ids;
unsigned char *buffer;
-#ifndef TCP_CHIMNEY_SUPPORT
unsigned int size = roundup_pow_of_two((limit - base) * sizeof(int));
-#else
- /* ### TODO - Linux kfifos really are a power of two, sysdep_ci2linux
- does ci_fifo2's, which only actually hold 2^n - 1.
- We need to double buffer size, not add one, because
- ci_fifo2 can only be a power of two. */
- unsigned int size = roundup_pow_of_two((limit - base) * 2 *
sizeof(int));
-#endif
-
EFRM_ASSERT(base <= limit);
buffer = vmalloc(size);
ids = kfifo_init(buffer, size, GFP_KERNEL, lock);
@@ -135,15 +110,9 @@ extern int
extern int
efrm_resource_manager_ctor(struct efrm_resource_manager *rm,
void (*dtor)(struct efrm_resource_manager *),
- const char *name, unsigned type,
- int initial_table_size);
+ const char *name, unsigned type);
extern void efrm_resource_manager_dtor(struct efrm_resource_manager *rm);
-/*! Insert a resource into table in the resource manager.
- *
- * Caller should free the resource if this function returns non-zero.
- */
-extern int efrm_resource_manager_insert(struct efrm_resource *rs);
#endif /* __CI_EFRM_PRIVATE_H__ */
diff -r 0b5ca7cdbdfc -r b8c2a9aacba6
drivers/net/sfc/sfc_resource/ci/efrm/resource.h
--- a/drivers/net/sfc/sfc_resource/ci/efrm/resource.h Fri Jan 08 13:05:49
2010 +0000
+++ b/drivers/net/sfc/sfc_resource/ci/efrm/resource.h Fri Jan 08 13:06:22
2010 +0000
@@ -5,7 +5,7 @@
*
* This file provides public interface of efrm library -- resource handling.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
@@ -62,9 +62,11 @@
/*! Representation of an allocated resource */
struct efrm_resource {
- atomic_t rs_ref_count; /*!< users count; see
- * __efrm_resource_ref_count_zero() */
+ int rs_ref_count;
efrm_resource_handle_t rs_handle;
+ struct efrm_client *rs_client;
+ struct list_head rs_client_link;
+ struct list_head rs_manager_link;
};
/*--------------------------------------------------------------------
@@ -82,9 +84,7 @@ struct efrm_resource_manager {
#endif
int rm_resources;
int rm_resources_hiwat;
- /*! table of allocated resources */
- struct efrm_resource **rm_table;
- unsigned rm_table_size;
+ struct list_head rm_resources_list;
/**
* Destructor for the resource manager. Other resource managers
* might be already dead, although the system guarantees that
@@ -111,12 +111,9 @@ extern void efrm_resource_manager_assert
efrm_resource_manager_assert_valid((rm), __FILE__, __LINE__)
#endif
-/*! Check the reference count on the resource provided and delete its
- * handle it in its owning resource manager if the
- * reference count has fallen to zero.
- *
- * Returns TRUE if the caller should really free the resource.
- */
-extern bool __efrm_resource_ref_count_zero(unsigned type, unsigned instance);
+
+extern void efrm_resource_ref(struct efrm_resource *rs);
+extern int __efrm_resource_release(struct efrm_resource *);
+
#endif /* __CI_EFRM_RESOURCE_H__ */
diff -r 0b5ca7cdbdfc -r b8c2a9aacba6
drivers/net/sfc/sfc_resource/ci/efrm/resource_id.h
--- a/drivers/net/sfc/sfc_resource/ci/efrm/resource_id.h Fri Jan 08
13:05:49 2010 +0000
+++ b/drivers/net/sfc/sfc_resource/ci/efrm/resource_id.h Fri Jan 08
13:06:22 2010 +0000
@@ -6,7 +6,7 @@
* This file provides public type and definitions resource handle, and the
* definitions of resource types.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
@@ -73,12 +73,12 @@ typedef struct {
static inline unsigned EFRM_RESOURCE_PRI_ARG(efrm_resource_handle_t h)
{
- return (h.handle);
+ return h.handle;
}
static inline unsigned EFRM_RESOURCE_INSTANCE(efrm_resource_handle_t h)
{
- return (h.handle & 0x0000ffff);
+ return h.handle & 0x0000ffff;
}
static inline unsigned EFRM_RESOURCE_TYPE(efrm_resource_handle_t h)
diff -r 0b5ca7cdbdfc -r b8c2a9aacba6
drivers/net/sfc/sfc_resource/ci/efrm/sysdep.h
--- a/drivers/net/sfc/sfc_resource/ci/efrm/sysdep.h Fri Jan 08 13:05:49
2010 +0000
+++ b/drivers/net/sfc/sfc_resource/ci/efrm/sysdep.h Fri Jan 08 13:06:22
2010 +0000
@@ -5,7 +5,7 @@
*
* This file provides Linux-like system-independent API for efrm library.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
@@ -41,8 +41,6 @@
/* Spinlocks are defined in efhw/sysdep.h */
#include <ci/efhw/sysdep.h>
-
-# include <ci/efrm/sysdep_linux.h>
-
+#include <ci/efrm/sysdep_linux.h>
#endif /* __CI_EFRM_SYSDEP_H__ */
diff -r 0b5ca7cdbdfc -r b8c2a9aacba6
drivers/net/sfc/sfc_resource/ci/efrm/sysdep_linux.h
--- a/drivers/net/sfc/sfc_resource/ci/efrm/sysdep_linux.h Fri Jan 08
13:05:49 2010 +0000
+++ b/drivers/net/sfc/sfc_resource/ci/efrm/sysdep_linux.h Fri Jan 08
13:06:22 2010 +0000
@@ -6,7 +6,7 @@
* This file provides version-independent Linux kernel API for efrm library.
* Only kernels >=2.6.9 are supported.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
@@ -75,7 +75,7 @@
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,9))
static inline unsigned long __attribute_const__ roundup_pow_of_two(unsigned
long x)
{
- return (1UL << fls(x - 1));
+ return 1UL << fls(x - 1);
}
#endif
@@ -145,13 +145,7 @@ typedef void (*efrm_old_work_func_t) (vo
*
********************************************************************/
-#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,10)
-
-#if !defined(RHEL_RELEASE_CODE) || (RHEL_RELEASE_CODE < 1029)
-typedef unsigned gfp_t;
-#endif
-
-#define HAS_NO_KFIFO
+#ifdef EFX_NEED_KFIFO
struct kfifo {
unsigned char *buffer; /* the buffer holding the data */
@@ -255,7 +249,7 @@ static inline unsigned int kfifo_len(str
}
#else
-#include <linux/kfifo.h>
+# include <linux/kfifo.h>
#endif
static inline void kfifo_vfree(struct kfifo *fifo)
diff -r 0b5ca7cdbdfc -r b8c2a9aacba6
drivers/net/sfc/sfc_resource/ci/efrm/vi_resource.h
--- a/drivers/net/sfc/sfc_resource/ci/efrm/vi_resource.h Fri Jan 08
13:05:49 2010 +0000
+++ b/drivers/net/sfc/sfc_resource/ci/efrm/vi_resource.h Fri Jan 08
13:06:22 2010 +0000
@@ -5,7 +5,7 @@
*
* This file contains public API for VI resource.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
@@ -64,40 +64,20 @@ efrm_resource *efrm_from_vi_resource(str
EFRM_RESOURCE_PRI_ARG(efrm_from_vi_resource(virs)->rs_handle)
extern int
-efrm_vi_resource_alloc(struct vi_resource *evq_virs,
- uint16_t vi_flags, int32_t evq_capacity,
- int32_t txq_capacity, int32_t rxq_capacity,
- uint8_t tx_q_tag, uint8_t rx_q_tag,
+efrm_vi_resource_alloc(struct efrm_client *client,
+ struct vi_resource *evq_virs,
+ unsigned vi_flags, int evq_capacity,
+ int txq_capacity, int rxq_capacity,
+ int tx_q_tag, int rx_q_tag,
struct vi_resource **virs_in_out,
uint32_t *out_io_mmap_bytes,
uint32_t *out_mem_mmap_bytes,
uint32_t *out_txq_capacity,
uint32_t *out_rxq_capacity);
-static inline void efrm_vi_resource_ref(struct vi_resource *virs)
-{
- atomic_inc(&efrm_from_vi_resource(virs)->rs_ref_count);
-}
+extern void efrm_vi_resource_free(struct vi_resource *);
+extern void efrm_vi_resource_release(struct vi_resource *);
-/* efrm_vi_resource_free should be called only if
- * __efrm_resource_ref_count_zero() returned true.
- * The easiest way is to call efrm_vi_resource_release() */
-extern void efrm_vi_resource_free(struct vi_resource *virs);
-static inline void efrm_vi_resource_release(struct vi_resource *virs)
-{
- unsigned id;
- struct efrm_resource *rs = efrm_from_vi_resource(virs);
-
- id = EFRM_RESOURCE_INSTANCE(rs->rs_handle);
-
- if (atomic_dec_and_test(&rs->rs_ref_count)) {
- if (__efrm_resource_ref_count_zero(EFRM_RESOURCE_VI, id)) {
- EFRM_ASSERT(EFRM_RESOURCE_INSTANCE(rs->rs_handle) ==
- id);
- efrm_vi_resource_free(virs);
- }
- }
-}
/*--------------------------------------------------------------------
*
@@ -106,7 +86,7 @@ static inline void efrm_vi_resource_rele
*--------------------------------------------------------------------*/
/*! Reset an event queue and clear any associated timers */
-extern void efrm_eventq_reset(struct vi_resource *virs, int nic_index);
+extern void efrm_eventq_reset(struct vi_resource *virs);
/*! Register a kernel-level handler for the event queue. This function is
* called whenever a timer expires, or whenever the event queue is woken
@@ -138,8 +118,7 @@ extern void efrm_eventq_kill_callback(st
/*! Ask the NIC to generate a wakeup when an event is next delivered. */
extern void efrm_eventq_request_wakeup(struct vi_resource *rs,
- unsigned current_ptr,
- unsigned nic_index);
+ unsigned current_ptr);
/*! Register a kernel-level handler for flush completions.
* \TODO Currently, it is unsafe to install a callback more than once.
@@ -153,27 +132,24 @@ efrm_vi_register_flush_callback(struct v
void (*handler)(void *),
void *arg);
-int efrm_vi_resource_flush_retry(struct vi_resource *virs);
-
/*! Comment? */
-extern int efrm_pt_flush(struct vi_resource *);
+extern void efrm_pt_flush(struct vi_resource *);
/*! Comment? */
extern int efrm_pt_pace(struct vi_resource *, unsigned int val);
uint32_t efrm_vi_rm_txq_bytes(struct vi_resource *virs
- /*,struct efhw_nic *nic */ );
+ /*,struct efhw_nic *nic */);
uint32_t efrm_vi_rm_rxq_bytes(struct vi_resource *virs
- /*,struct efhw_nic *nic */ );
+ /*,struct efhw_nic *nic */);
uint32_t efrm_vi_rm_evq_bytes(struct vi_resource *virs
- /*,struct efhw_nic *nic */ );
+ /*,struct efhw_nic *nic */);
/* Fill [out_vi_data] with information required to allow a VI to be init'd.
* [out_vi_data] must ref at least VI_MAPPINGS_SIZE bytes.
*/
-extern void efrm_vi_resource_mappings(struct vi_resource*, int nic_i,
- void* out_vi_data);
+extern void efrm_vi_resource_mappings(struct vi_resource *, void *out_vi_data);
#endif /* __CI_EFRM_VI_RESOURCE_H__ */
diff -r 0b5ca7cdbdfc -r b8c2a9aacba6
drivers/net/sfc/sfc_resource/ci/efrm/vi_resource_manager.h
--- a/drivers/net/sfc/sfc_resource/ci/efrm/vi_resource_manager.h Fri Jan
08 13:05:49 2010 +0000
+++ b/drivers/net/sfc/sfc_resource/ci/efrm/vi_resource_manager.h Fri Jan
08 13:06:22 2010 +0000
@@ -7,7 +7,7 @@
* may be used outside of the SFC resource driver, but such use is not
* recommended.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
@@ -36,7 +36,7 @@
#include <ci/efhw/common.h>
#include <ci/efrm/vi_resource.h>
-#include <ci/efrm/nic_set.h>
+
#define EFRM_VI_RM_DMA_QUEUE_COUNT 2
#define EFRM_VI_RM_DMA_QUEUE_TX 0
@@ -57,17 +57,12 @@ enum {
#define VI_RESOURCE_EVQ_STATE(X) \
(((int32_t)1) << (VI_RESOURCE_EVQ_STATE_##X))
-/** Information about an event queue. */
-struct vi_resource_evq_info {
- /** Flag bits indicating the state of wakeups. */
- unsigned long evq_state;
- /** A pointer to the resource instance for this queue. This member
- * is only valid if evq_state is non-zero or the resource is known
- * to have a non-zero reference count. */
- struct vi_resource *evq_virs;
-};
+#ifdef __ci_ul_driver__
+#define EFRM_VI_USE_WORKQUEUE 0
+#else
#define EFRM_VI_USE_WORKQUEUE 1
+#endif
/*! Global information for the VI resource manager. */
struct vi_resource_manager {
@@ -81,7 +76,6 @@ struct vi_resource_manager {
int with_interrupt_limit;
bool iscsi_dmaq_instance_is_free;
- struct vi_resource_evq_info *evq_infos;
/* We keep VI resources which need flushing on these lists. The VI
* is put on the outstanding list when the flush request is issued
@@ -108,12 +102,6 @@ struct vi_resource_manager {
#endif
};
-struct vi_resource_nic_info {
- struct eventq_resource_hardware evq_pages;
-#if defined(__CI_HARDWARE_CONFIG_FALCON__)
- struct efhw_iopages dmaq_pages[EFRM_VI_RM_DMA_QUEUE_COUNT];
-#endif
-};
struct vi_resource {
/* Some macros make the assumption that the struct efrm_resource is
@@ -121,16 +109,13 @@ struct vi_resource {
struct efrm_resource rs;
atomic_t evq_refs; /*!< Number of users of the event queue. */
- efrm_nic_set_t nic_set;
-
uint32_t bar_mmap_bytes;
uint32_t mem_mmap_bytes;
- int32_t evq_capacity;
- int32_t dmaq_capacity[EFRM_VI_RM_DMA_QUEUE_COUNT];
-
+ int evq_capacity;
+ int dmaq_capacity[EFRM_VI_RM_DMA_QUEUE_COUNT];
uint8_t dmaq_tag[EFRM_VI_RM_DMA_QUEUE_COUNT];
- uint16_t flags;
+ unsigned flags;
/* we keep PT endpoints that have been destroyed on a list
* until we have seen their TX and RX DMAQs flush complete
@@ -138,9 +123,9 @@ struct vi_resource {
*/
struct list_head rx_flush_link;
struct list_head tx_flush_link;
- efrm_nic_set_t rx_flush_nic_set;
- efrm_nic_set_t rx_flush_outstanding_nic_set;
- efrm_nic_set_t tx_flush_nic_set;
+ int rx_flushing;
+ int rx_flush_outstanding;
+ int tx_flushing;
uint64_t flush_time;
int flush_count;
@@ -153,26 +138,14 @@ struct vi_resource {
struct vi_resource *evq_virs; /*!< EVQ for DMA queues */
-#if defined(__CI_HARDWARE_CONFIG_FALCON__)
- struct efhw_buffer_table_allocation
- dmaq_buf_tbl_alloc[EFRM_VI_RM_DMA_QUEUE_COUNT];
-#endif
-
- struct vi_resource_nic_info nic_info[EFHW_MAX_NR_DEVS];
+ struct eventq_resource_hardware evq_hw;
+ struct efhw_iopages dmaq_pages[EFRM_VI_RM_DMA_QUEUE_COUNT];
+ struct efhw_buffer_table_allocation
+ dmaq_buf_tbl_alloc[EFRM_VI_RM_DMA_QUEUE_COUNT];
};
#undef vi_resource
#define vi_resource(rs1) container_of((rs1), struct vi_resource, rs)
-static inline dma_addr_t
-efrm_eventq_dma_addr(struct vi_resource *virs, uint32_t nic_index)
-{
- struct eventq_resource_hardware *hw;
- EFRM_ASSERT(efrm_nic_set_read(&virs->nic_set, nic_index));
-
- hw = &(virs->nic_info[nic_index].evq_pages);
-
- return efhw_iopages_dma_addr(&(hw->iobuff)) + hw->iobuff_off;
-}
#endif /* __CI_DRIVER_EFAB_VI_RESOURCE_MANAGER_H__ */
diff -r 0b5ca7cdbdfc -r b8c2a9aacba6
drivers/net/sfc/sfc_resource/ci/efrm/vi_resource_private.h
--- a/drivers/net/sfc/sfc_resource/ci/efrm/vi_resource_private.h Fri Jan
08 13:05:49 2010 +0000
+++ b/drivers/net/sfc/sfc_resource/ci/efrm/vi_resource_private.h Fri Jan
08 13:06:22 2010 +0000
@@ -6,7 +6,7 @@
* This file contains private API for VI resource. The API is not designed
* to be used outside of the SFC resource driver.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
@@ -49,27 +49,6 @@ void efrm_vi_rm_init_dmaq(struct vi_reso
void efrm_vi_rm_init_dmaq(struct vi_resource *virs, int queue_index,
struct efhw_nic *nic);
-static inline int
-efrm_eventq_bytes(struct vi_resource *virs, uint32_t nic_index)
-{
- EFRM_ASSERT(efrm_nic_set_read(&virs->nic_set, nic_index));
-
- return efrm_vi_rm_evq_bytes(virs);
-}
-
-static inline efhw_event_t *
-efrm_eventq_base(struct vi_resource *virs, uint32_t nic_index)
-{
- struct eventq_resource_hardware *hw;
-
- EFRM_ASSERT(efrm_nic_set_read(&virs->nic_set, nic_index));
-
- hw = &(virs->nic_info[nic_index].evq_pages);
-
- return (efhw_event_t *) (efhw_iopages_ptr(&(hw->iobuff)) +
- hw->iobuff_off);
-}
-
/*! Wakeup handler */
extern void efrm_handle_wakeup_event(struct efhw_nic *nic, unsigned id);
@@ -78,7 +57,7 @@ extern void efrm_handle_timeout_event(st
/*! DMA flush handler */
extern void efrm_handle_dmaq_flushed(struct efhw_nic *nic, unsigned id,
- int rx_flush);
+ int rx_flush, int failed);
/*! SRAM update handler */
extern void efrm_handle_sram_event(struct efhw_nic *nic);
diff -r 0b5ca7cdbdfc -r b8c2a9aacba6
drivers/net/sfc/sfc_resource/driver_object.c
--- a/drivers/net/sfc/sfc_resource/driver_object.c Fri Jan 08 13:05:49
2010 +0000
+++ b/drivers/net/sfc/sfc_resource/driver_object.c Fri Jan 08 13:06:22
2010 +0000
@@ -5,7 +5,7 @@
*
* This file contains support for the global driver variables.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
@@ -38,6 +38,9 @@
#include <ci/efrm/nic_table.h>
#include <ci/efrm/resource.h>
#include <ci/efrm/debug.h>
+#include <ci/efrm/efrm_client.h>
+#include <ci/efrm/efrm_nic.h>
+#include "efrm_internal.h"
/* We use #define rather than static inline here so that the Windows
* "prefast" compiler can see its own locking primitive when these
@@ -66,6 +69,7 @@ static struct efrm_nic_table efrm_nic_ta
static struct efrm_nic_table efrm_nic_table;
struct efrm_nic_table *efrm_nic_tablep;
EXPORT_SYMBOL(efrm_nic_tablep);
+
/* Internal table with resource managers.
* We'd like to not export it, but we are still using efrm_rm_table
@@ -74,67 +78,89 @@ struct efrm_resource_manager *efrm_rm_ta
struct efrm_resource_manager *efrm_rm_table[EFRM_RESOURCE_NUM];
EXPORT_SYMBOL(efrm_rm_table);
-int efrm_driver_ctor(void)
-{
- efrm_nic_tablep = &efrm_nic_table;
+
+/* List of registered nics. */
+static LIST_HEAD(efrm_nics);
+
+
+void efrm_driver_ctor(void)
+{
+ efrm_nic_tablep = &efrm_nic_table;
spin_lock_init(&efrm_nic_tablep->lock);
-
EFRM_TRACE("%s: driver created", __FUNCTION__);
- return 0;
-}
-
-int efrm_driver_dtor(void)
+}
+
+void efrm_driver_dtor(void)
{
EFRM_ASSERT(!efrm_nic_table_held());
spin_lock_destroy(&efrm_nic_tablep->lock);
memset(&efrm_nic_table, 0, sizeof(efrm_nic_table));
memset(&efrm_rm_table, 0, sizeof(efrm_rm_table));
-
EFRM_TRACE("%s: driver deleted", __FUNCTION__);
- return 0;
-}
-
-int efrm_driver_register_nic(struct efhw_nic *nic, int nic_index)
-{
- int rc = 0;
+}
+
+int efrm_driver_register_nic(struct efrm_nic *rnic, int nic_index,
+ int ifindex)
+{
+ struct efhw_nic *nic = &rnic->efhw_nic;
+ struct efrm_nic_per_vi *vis;
+ int max_vis, rc = 0;
irq_flags_t lock_flags;
EFRM_ASSERT(nic_index >= 0);
+ EFRM_ASSERT(ifindex >= 0);
+
+ max_vis = 4096; /* TODO: Get runtime value. */
+ vis = vmalloc(max_vis * sizeof(rnic->vis[0]));
+ if (vis == NULL) {
+ EFRM_ERR("%s: Out of memory", __FUNCTION__);
+ return -ENOMEM;
+ }
+ memset(vis, 0, max_vis * sizeof(vis[0]));
efrm_driver_lock(lock_flags);
if (efrm_nic_table_held()) {
- EFRM_WARN("%s: driver object is in use", __FUNCTION__);
+ EFRM_ERR("%s: driver object is in use", __FUNCTION__);
rc = -EBUSY;
goto done;
}
if (efrm_nic_tablep->nic_count == EFHW_MAX_NR_DEVS) {
- EFRM_WARN("%s: filled up NIC table size %d", __FUNCTION__,
- EFHW_MAX_NR_DEVS);
+ EFRM_ERR("%s: filled up NIC table size %d", __FUNCTION__,
+ EFHW_MAX_NR_DEVS);
rc = -E2BIG;
goto done;
}
+
+ rnic->vis = vis;
EFRM_ASSERT(efrm_nic_tablep->nic[nic_index] == NULL);
efrm_nic_tablep->nic[nic_index] = nic;
nic->index = nic_index;
+ nic->ifindex = ifindex;
if (efrm_nic_tablep->a_nic == NULL)
efrm_nic_tablep->a_nic = nic;
efrm_nic_tablep->nic_count++;
+
+ INIT_LIST_HEAD(&rnic->clients);
+ list_add(&rnic->link, &efrm_nics);
+
efrm_driver_unlock(lock_flags);
- return rc;
+ return 0;
done:
efrm_driver_unlock(lock_flags);
+ vfree(vis);
return rc;
}
-int efrm_driver_unregister_nic(struct efhw_nic *nic)
-{
+int efrm_driver_unregister_nic(struct efrm_nic *rnic)
+{
+ struct efhw_nic *nic = &rnic->efhw_nic;
int rc = 0;
int nic_index = nic->index;
irq_flags_t lock_flags;
@@ -144,12 +170,20 @@ int efrm_driver_unregister_nic(struct ef
efrm_driver_lock(lock_flags);
if (efrm_nic_table_held()) {
- EFRM_WARN("%s: driver object is in use", __FUNCTION__);
+ EFRM_ERR("%s: driver object is in use", __FUNCTION__);
rc = -EBUSY;
goto done;
}
+ if (!list_empty(&rnic->clients)) {
+ EFRM_ERR("%s: nic has active clients", __FUNCTION__);
+ rc = -EBUSY;
+ goto done;
+ }
EFRM_ASSERT(efrm_nic_tablep->nic[nic_index] == nic);
+ EFRM_ASSERT(list_empty(&rnic->clients));
+
+ list_del(&rnic->link);
nic->index = -1;
efrm_nic_tablep->nic[nic_index] = NULL;
@@ -174,3 +208,135 @@ done:
efrm_driver_unlock(lock_flags);
return rc;
}
+
+
+#ifdef __KERNEL__
+
+
+int efrm_nic_pre_reset(struct efhw_nic *nic)
+{
+ struct efrm_nic *rnic = efrm_nic(nic);
+ struct efrm_client *client;
+ struct efrm_resource *rs;
+ struct list_head *client_link;
+ struct list_head *rs_link;
+ irq_flags_t lock_flags;
+
+ spin_lock_irqsave(&efrm_nic_tablep->lock, lock_flags);
+ list_for_each(client_link, &rnic->clients) {
+ client = container_of(client_link, struct efrm_client, link);
+ EFRM_ERR("%s: client %p", __FUNCTION__, client);
+ if (client->callbacks->pre_reset)
+ client->callbacks->pre_reset(client, client->user_data);
+ list_for_each(rs_link, &client->resources) {
+ rs = container_of(rs_link, struct efrm_resource,
+ rs_client_link);
+ EFRM_ERR("%s: resource %p", __FUNCTION__, rs);
+ /* TODO: mark rs defunct */
+ }
+ }
+ spin_unlock_irqrestore(&efrm_nic_tablep->lock, lock_flags);
+
+ return 0;
+}
+
+
+int efrm_nic_stop(struct efhw_nic *nic)
+{
+ /* TODO */
+ return 0;
+}
+
+
+int efrm_nic_resume(struct efhw_nic *nic)
+{
+ /* TODO */
+ return 0;
+}
+
+
+static void efrm_client_nullcb(struct efrm_client *client, void *user_data)
+{
+}
+
+static struct efrm_client_callbacks efrm_null_callbacks = {
+ efrm_client_nullcb,
+ efrm_client_nullcb,
+ efrm_client_nullcb
+};
+
+
+int efrm_client_get(int ifindex, struct efrm_client_callbacks *callbacks,
+ void *user_data, struct efrm_client **client_out)
+{
+ struct efrm_nic *n, *rnic = NULL;
+ irq_flags_t lock_flags;
+ struct list_head *link;
+ struct efrm_client *client;
+
+ if (callbacks == NULL)
+ callbacks = &efrm_null_callbacks;
+
+ client = kmalloc(sizeof(*client), GFP_KERNEL);
+ if (client == NULL)
+ return -ENOMEM;
+
+ spin_lock_irqsave(&efrm_nic_tablep->lock, lock_flags);
+ list_for_each(link, &efrm_nics) {
+ n = container_of(link, struct efrm_nic, link);
+ if (n->efhw_nic.ifindex == ifindex || ifindex < 0) {
+ rnic = n;
+ break;
+ }
+ }
+ if (rnic) {
+ client->user_data = user_data;
+ client->callbacks = callbacks;
+ client->nic = &rnic->efhw_nic;
+ client->ref_count = 1;
+ INIT_LIST_HEAD(&client->resources);
+ list_add(&client->link, &rnic->clients);
+ }
+ spin_unlock_irqrestore(&efrm_nic_tablep->lock, lock_flags);
+
+ if (rnic == NULL)
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