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[Xen-changelog] [xen-3.4-testing] i386: fix full-value calculation of wr

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Subject: [Xen-changelog] [xen-3.4-testing] i386: fix full-value calculation of wrmsr handling for pv guests
From: "Xen patchbot-3.4-testing" <patchbot-3.4-testing@xxxxxxxxxxxxxxxxxxx>
Date: Tue, 04 Aug 2009 08:50:54 -0700
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# HG changeset patch
# User Keir Fraser <keir.fraser@xxxxxxxxxx>
# Date 1248973186 -3600
# Node ID a6159337c577cfe9400dd8574e21b96a6d9ca733
# Parent  a5509916d4f6aaa5526f856590ae06e631fb5d01
i386: fix full-value calculation of wrmsr handling for pv guests

The MSR value must be held in a 64-bit variable, not an unsigned long.

Signed-off-by: Jan Beulich <jbeulich@xxxxxxxxxx>
Signed-off-by: Keir Fraser <keir.fraser@xxxxxxxxxx>
xen-unstable changeset:   20002:e6c966b3a4d8
xen-unstable date:        Thu Jul 30 17:56:23 2009 +0100
---
 xen/arch/x86/traps.c |   27 +++++++++++++++------------
 1 files changed, 15 insertions(+), 12 deletions(-)

diff -r a5509916d4f6 -r a6159337c577 xen/arch/x86/traps.c
--- a/xen/arch/x86/traps.c      Wed Jul 29 14:21:26 2009 +0100
+++ b/xen/arch/x86/traps.c      Thu Jul 30 17:59:46 2009 +0100
@@ -1648,7 +1648,7 @@ static int emulate_privileged_op(struct 
 static int emulate_privileged_op(struct cpu_user_regs *regs)
 {
     struct vcpu *v = current;
-    unsigned long *reg, eip = regs->eip, res;
+    unsigned long *reg, eip = regs->eip;
     u8 opcode, modrm_reg = 0, modrm_rm = 0, rep_prefix = 0, lock = 0, rex = 0;
     enum { lm_seg_none, lm_seg_fs, lm_seg_gs } lm_ovr = lm_seg_none;
     unsigned int port, i, data_sel, ar, data, rc, bpmatch = 0;
@@ -1666,7 +1666,7 @@ static int emulate_privileged_op(struct 
     unsigned long code_base, code_limit;
     char io_emul_stub[32];
     void (*io_emul)(struct cpu_user_regs *) __attribute__((__regparm__(1)));
-    u32 l, h, eax, edx;
+    u32 l, h;
 
     if ( !read_descriptor(regs->cs, v, regs,
                           &code_base, &code_limit, &ar,
@@ -2045,7 +2045,8 @@ static int emulate_privileged_op(struct 
         }
         break;
 
-    case 0x21: /* MOV DR?,<reg> */
+    case 0x21: /* MOV DR?,<reg> */ {
+        unsigned long res;
         opcode = insn_fetch(u8, code_base, eip, code_limit);
         if ( opcode < 0xc0 )
             goto fail;
@@ -2056,6 +2057,7 @@ static int emulate_privileged_op(struct 
             goto fail;
         *reg = res;
         break;
+    }
 
     case 0x22: /* MOV <reg>,CR? */
         opcode = insn_fetch(u8, code_base, eip, code_limit);
@@ -2116,10 +2118,10 @@ static int emulate_privileged_op(struct 
             goto fail;
         break;
 
-    case 0x30: /* WRMSR */
-        eax = regs->eax;
-        edx = regs->edx;
-        res = ((u64)edx << 32) | eax;
+    case 0x30: /* WRMSR */ {
+        u32 eax = regs->eax;
+        u32 edx = regs->edx;
+        u64 val = ((u64)edx << 32) | eax;
         switch ( (u32)regs->ecx )
         {
 #ifdef CONFIG_X86_64
@@ -2128,21 +2130,21 @@ static int emulate_privileged_op(struct 
                 goto fail;
             if ( wrmsr_safe(MSR_FS_BASE, eax, edx) )
                 goto fail;
-            v->arch.guest_context.fs_base = res;
+            v->arch.guest_context.fs_base = val;
             break;
         case MSR_GS_BASE:
             if ( is_pv_32on64_vcpu(v) )
                 goto fail;
             if ( wrmsr_safe(MSR_GS_BASE, eax, edx) )
                 goto fail;
-            v->arch.guest_context.gs_base_kernel = res;
+            v->arch.guest_context.gs_base_kernel = val;
             break;
         case MSR_SHADOW_GS_BASE:
             if ( is_pv_32on64_vcpu(v) )
                 goto fail;
             if ( wrmsr_safe(MSR_SHADOW_GS_BASE, eax, edx) )
                 goto fail;
-            v->arch.guest_context.gs_base_user = res;
+            v->arch.guest_context.gs_base_user = val;
             break;
 #endif
         case MSR_K7_FID_VID_STATUS:
@@ -2185,7 +2187,7 @@ static int emulate_privileged_op(struct 
             if ( !IS_PRIV(v->domain) )
                 break;
             if ( (rdmsr_safe(MSR_FAM10H_MMIO_CONF_BASE, l, h) != 0) ||
-                 (((((u64)h << 32) | l) ^ res) &
+                 (((((u64)h << 32) | l) ^ val) &
                   ~((1 << FAM10H_MMIO_CONF_ENABLE_BIT) |
                     (FAM10H_MMIO_CONF_BUSRANGE_MASK <<
                      FAM10H_MMIO_CONF_BUSRANGE_SHIFT) |
@@ -2218,7 +2220,7 @@ static int emulate_privileged_op(struct 
                 break;
             if ( boot_cpu_data.x86_vendor == X86_VENDOR_INTEL )
             {
-                int rc = intel_mce_wrmsr(regs->ecx, res);
+                int rc = intel_mce_wrmsr(regs->ecx, val);
                 if ( rc < 0 )
                     goto fail;
                 if ( rc )
@@ -2234,6 +2236,7 @@ static int emulate_privileged_op(struct 
             break;
         }
         break;
+    }
 
     case 0x31: /* RDTSC */
         rdtsc(regs->eax, regs->edx);

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