# HG changeset patch
# User Keir Fraser <keir.fraser@xxxxxxxxxx>
# Date 1238502525 -3600
# Node ID 0faf7b884711a958d9073edb64d191d9a07fc064
# Parent d7bf5a03cf074cc6213b1c79478c4b14041e0867
x86: Enable S3 for 32bit dom0 on 64bit Xen
Three SYSENTER MSRs should be taken care of at save/restore BSP
context, or else 32bit dom0 rejects working after S3 resume. Thanks
for Jan's help to find this missing part.
Signed-off-by: Guanqun Lu <guanqun.lu@xxxxxxxxx>
Signed-off-by: Kevin Tian <kevin.tian@xxxxxxxxx>
---
xen/arch/x86/acpi/suspend.c | 14 ++++++++++++++
1 files changed, 14 insertions(+)
diff -r d7bf5a03cf07 -r 0faf7b884711 xen/arch/x86/acpi/suspend.c
--- a/xen/arch/x86/acpi/suspend.c Tue Mar 31 13:27:03 2009 +0100
+++ b/xen/arch/x86/acpi/suspend.c Tue Mar 31 13:28:45 2009 +0100
@@ -16,6 +16,7 @@
#if defined(CONFIG_X86_64)
static unsigned long saved_lstar, saved_cstar;
+static unsigned long saved_sysenter_esp, saved_sysenter_eip;
#endif
void save_rest_processor_state(void)
@@ -26,6 +27,11 @@ void save_rest_processor_state(void)
#if defined(CONFIG_X86_64)
rdmsrl(MSR_CSTAR, saved_cstar);
rdmsrl(MSR_LSTAR, saved_lstar);
+ if ( boot_cpu_data.x86_vendor == X86_VENDOR_INTEL )
+ {
+ rdmsrl(MSR_IA32_SYSENTER_ESP, saved_sysenter_esp);
+ rdmsrl(MSR_IA32_SYSENTER_EIP, saved_sysenter_eip);
+ }
#endif
}
@@ -41,6 +47,14 @@ void restore_rest_processor_state(void)
wrmsrl(MSR_CSTAR, saved_cstar);
wrmsr(MSR_STAR, 0, (FLAT_RING3_CS32<<16) | __HYPERVISOR_CS);
wrmsr(MSR_SYSCALL_MASK, EF_VM|EF_RF|EF_NT|EF_DF|EF_IE|EF_TF, 0U);
+
+ if ( boot_cpu_data.x86_vendor == X86_VENDOR_INTEL )
+ {
+ /* Recover sysenter MSRs */
+ wrmsrl(MSR_IA32_SYSENTER_ESP, saved_sysenter_esp);
+ wrmsrl(MSR_IA32_SYSENTER_EIP, saved_sysenter_eip);
+ wrmsr(MSR_IA32_SYSENTER_CS, __HYPERVISOR_CS, 0);
+ }
#else /* !defined(CONFIG_X86_64) */
if ( supervisor_mode_kernel && cpu_has_sep )
wrmsr(MSR_IA32_SYSENTER_ESP, &init_tss[smp_processor_id()].esp1, 0);
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