[Xen-changelog] [xen-unstable] NMI watchdog: don't try to run too slow.

[Xen patchbot-unstable <patchbot-unstable@xxxxxxxxxxxxxxxxxxx>]

# HG changeset patch
# User Keir Fraser <keir.fraser@xxxxxxxxxx>
# Date 1224511879 -3600
# Node ID 314df03b7d61773dc65c076e049960fa0e39ca07
# Parent  0a09de68c54153243d9293c82cbb6ddca4e4a76d
NMI watchdog: don't try to run too slow.

The way MSR writes of performance counters works means that Intel
CPUs running faster than about 2.1GHz can't set the NMI timer to 1Hz.

Signed-off-by: Tim Deegan <Tim.Deegan@xxxxxxxxxx>
---
 xen/arch/x86/nmi.c |   13 ++++++++++---
 1 files changed, 10 insertions(+), 3 deletions(-)

diff -r 0a09de68c541 -r 314df03b7d61 xen/arch/x86/nmi.c
--- a/xen/arch/x86/nmi.c        Mon Oct 20 15:08:24 2008 +0100
+++ b/xen/arch/x86/nmi.c        Mon Oct 20 15:11:19 2008 +0100
@@ -122,10 +122,17 @@ int __init check_nmi_watchdog (void)
 
     printk("\n");
 
-    /* now that we know it works we can reduce NMI frequency to
-       something more reasonable; makes a difference in some configs */
+    /*
+     * Now that we know it works we can reduce NMI frequency to
+     * something more reasonable; makes a difference in some configs.
+     * There's a limit to how slow we can go because writing the perfctr
+     * MSRs only sets the low 32 bits, with the top 8 bits sign-extended
+     * from those, so it's not possible to set up a delay larger than
+     * 2^31 cycles and smaller than (2^40 - 2^31) cycles. 
+     * (Intel SDM, section 18.22.2)
+     */
     if ( nmi_watchdog == NMI_LOCAL_APIC )
-        nmi_hz = 1;
+        nmi_hz = max(1ul, cpu_khz >> 20);
 
     return 0;
 }

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