# HG changeset patch
# User Isaku Yamahata <yamahata@xxxxxxxxxxxxx>
# Date 1223608021 -32400
# Node ID 9010d63470ffd5136da7e2a9750f18cef705788e
# Parent 55ec2b18fe7f1877cedf5ff367e7c05cdcdebb66
# Parent 2b5cc22ab4063a1edf1a78348a916b0f116afbda
merge with linux-2.6.18-xen.hg
---
arch/i386/kernel/cpu/amd.c | 16 +------
arch/i386/kernel/cpu/centaur.c | 34 +++++-----------
arch/i386/kernel/cpu/common.c | 4 -
arch/i386/kernel/cpu/cyrix.c | 57 +++++++++------------------
arch/i386/kernel/cpu/intel.c | 2
arch/i386/kernel/cpu/nexgen.c | 14 ------
arch/i386/kernel/cpu/rise.c | 13 ------
arch/i386/kernel/cpu/transmeta.c | 14 ------
arch/i386/kernel/cpu/umc.c | 17 --------
arch/x86_64/mm/init-xen.c | 4 -
drivers/pci/Makefile | 3 -
drivers/pci/msi-xen.c | 3 -
drivers/pci/pci.h | 5 ++
drivers/pci/quirks.c | 49 +++++++++++++++++++++++
drivers/pci/reassigndev.c | 80 ++++++++++++++++++++++++++++++++++++++
drivers/pci/setup-bus.c | 9 +++-
drivers/pci/setup-res.c | 82 ++++++++++++++++++++++++++++++++++++++-
drivers/xen/core/evtchn.c | 13 +++++-
18 files changed, 285 insertions(+), 134 deletions(-)
diff -r 55ec2b18fe7f -r 9010d63470ff arch/i386/kernel/cpu/amd.c
--- a/arch/i386/kernel/cpu/amd.c Thu Oct 09 15:23:54 2008 +0900
+++ b/arch/i386/kernel/cpu/amd.c Fri Oct 10 12:07:01 2008 +0900
@@ -22,7 +22,7 @@ extern void vide(void);
extern void vide(void);
__asm__(".align 4\nvide: ret");
-static void __init init_amd(struct cpuinfo_x86 *c)
+static void __cpuinit init_amd(struct cpuinfo_x86 *c)
{
u32 l, h;
int mbytes = num_physpages >> (20-PAGE_SHIFT);
@@ -246,7 +246,7 @@ static void __init init_amd(struct cpuin
num_cache_leaves = 3;
}
-static unsigned int amd_size_cache(struct cpuinfo_x86 * c, unsigned int size)
+static unsigned int __cpuinit amd_size_cache(struct cpuinfo_x86 * c, unsigned
int size)
{
/* AMD errata T13 (order #21922) */
if ((c->x86 == 6)) {
@@ -259,7 +259,7 @@ static unsigned int amd_size_cache(struc
return size;
}
-static struct cpu_dev amd_cpu_dev __initdata = {
+static struct cpu_dev amd_cpu_dev __cpuinitdata = {
.c_vendor = "AMD",
.c_ident = { "AuthenticAMD" },
.c_models = {
@@ -284,13 +284,3 @@ int __init amd_init_cpu(void)
cpu_devs[X86_VENDOR_AMD] = &amd_cpu_dev;
return 0;
}
-
-//early_arch_initcall(amd_init_cpu);
-
-static int __init amd_exit_cpu(void)
-{
- cpu_devs[X86_VENDOR_AMD] = NULL;
- return 0;
-}
-
-late_initcall(amd_exit_cpu);
diff -r 55ec2b18fe7f -r 9010d63470ff arch/i386/kernel/cpu/centaur.c
--- a/arch/i386/kernel/cpu/centaur.c Thu Oct 09 15:23:54 2008 +0900
+++ b/arch/i386/kernel/cpu/centaur.c Fri Oct 10 12:07:01 2008 +0900
@@ -9,7 +9,7 @@
#ifdef CONFIG_X86_OOSTORE
-static u32 __init power2(u32 x)
+static u32 __cpuinit power2(u32 x)
{
u32 s=1;
while(s<=x)
@@ -22,7 +22,7 @@ static u32 __init power2(u32 x)
* Set up an actual MCR
*/
-static void __init centaur_mcr_insert(int reg, u32 base, u32 size, int key)
+static void __cpuinit centaur_mcr_insert(int reg, u32 base, u32 size, int key)
{
u32 lo, hi;
@@ -40,7 +40,7 @@ static void __init centaur_mcr_insert(in
* Shortcut: We know you can't put 4Gig of RAM on a winchip
*/
-static u32 __init ramtop(void) /* 16388 */
+static u32 __cpuinit ramtop(void) /* 16388 */
{
int i;
u32 top = 0;
@@ -91,7 +91,7 @@ static u32 __init ramtop(void) /* 16388
* Compute a set of MCR's to give maximum coverage
*/
-static int __init centaur_mcr_compute(int nr, int key)
+static int __cpuinit centaur_mcr_compute(int nr, int key)
{
u32 mem = ramtop();
u32 root = power2(mem);
@@ -166,7 +166,7 @@ static int __init centaur_mcr_compute(in
return ct;
}
-static void __init centaur_create_optimal_mcr(void)
+static void __cpuinit centaur_create_optimal_mcr(void)
{
int i;
/*
@@ -189,7 +189,7 @@ static void __init centaur_create_optima
wrmsr(MSR_IDT_MCR0+i, 0, 0);
}
-static void __init winchip2_create_optimal_mcr(void)
+static void __cpuinit winchip2_create_optimal_mcr(void)
{
u32 lo, hi;
int i;
@@ -227,7 +227,7 @@ static void __init winchip2_create_optim
* Handle the MCR key on the Winchip 2.
*/
-static void __init winchip2_unprotect_mcr(void)
+static void __cpuinit winchip2_unprotect_mcr(void)
{
u32 lo, hi;
u32 key;
@@ -239,7 +239,7 @@ static void __init winchip2_unprotect_mc
wrmsr(MSR_IDT_MCR_CTRL, lo, hi);
}
-static void __init winchip2_protect_mcr(void)
+static void __cpuinit winchip2_protect_mcr(void)
{
u32 lo, hi;
@@ -257,7 +257,7 @@ static void __init winchip2_protect_mcr(
#define RNG_ENABLED (1 << 3)
#define RNG_ENABLE (1 << 6) /* MSR_VIA_RNG */
-static void __init init_c3(struct cpuinfo_x86 *c)
+static void __cpuinit init_c3(struct cpuinfo_x86 *c)
{
u32 lo, hi;
@@ -303,7 +303,7 @@ static void __init init_c3(struct cpuinf
display_cacheinfo(c);
}
-static void __init init_centaur(struct cpuinfo_x86 *c)
+static void __cpuinit init_centaur(struct cpuinfo_x86 *c)
{
enum {
ECX8=1<<1,
@@ -442,7 +442,7 @@ static void __init init_centaur(struct c
}
}
-static unsigned int centaur_size_cache(struct cpuinfo_x86 * c, unsigned int
size)
+static unsigned int __cpuinit centaur_size_cache(struct cpuinfo_x86 * c,
unsigned int size)
{
/* VIA C3 CPUs (670-68F) need further shifting. */
if ((c->x86 == 6) && ((c->x86_model == 7) || (c->x86_model == 8)))
@@ -457,7 +457,7 @@ static unsigned int centaur_size_cache(s
return size;
}
-static struct cpu_dev centaur_cpu_dev __initdata = {
+static struct cpu_dev centaur_cpu_dev __cpuinitdata = {
.c_vendor = "Centaur",
.c_ident = { "CentaurHauls" },
.c_init = init_centaur,
@@ -469,13 +469,3 @@ int __init centaur_init_cpu(void)
cpu_devs[X86_VENDOR_CENTAUR] = ¢aur_cpu_dev;
return 0;
}
-
-//early_arch_initcall(centaur_init_cpu);
-
-static int __init centaur_exit_cpu(void)
-{
- cpu_devs[X86_VENDOR_CENTAUR] = NULL;
- return 0;
-}
-
-late_initcall(centaur_exit_cpu);
diff -r 55ec2b18fe7f -r 9010d63470ff arch/i386/kernel/cpu/common.c
--- a/arch/i386/kernel/cpu/common.c Thu Oct 09 15:23:54 2008 +0900
+++ b/arch/i386/kernel/cpu/common.c Fri Oct 10 12:07:01 2008 +0900
@@ -36,7 +36,7 @@ struct cpu_dev * cpu_devs[X86_VENDOR_NUM
extern int disable_pse;
-static void default_init(struct cpuinfo_x86 * c)
+static void __cpuinit default_init(struct cpuinfo_x86 * c)
{
/* Not much we can do here... */
/* Check if at least it has cpuid */
@@ -49,7 +49,7 @@ static void default_init(struct cpuinfo_
}
}
-static struct cpu_dev default_cpu = {
+static struct cpu_dev __cpuinitdata default_cpu = {
.c_init = default_init,
.c_vendor = "Unknown",
};
diff -r 55ec2b18fe7f -r 9010d63470ff arch/i386/kernel/cpu/cyrix.c
--- a/arch/i386/kernel/cpu/cyrix.c Thu Oct 09 15:23:54 2008 +0900
+++ b/arch/i386/kernel/cpu/cyrix.c Fri Oct 10 12:07:01 2008 +0900
@@ -52,25 +52,25 @@ static void __init do_cyrix_devid(unsign
* Actually since bugs.h doesn't even reference this perhaps someone should
* fix the documentation ???
*/
-static unsigned char Cx86_dir0_msb __initdata = 0;
-
-static char Cx86_model[][9] __initdata = {
+static unsigned char Cx86_dir0_msb __cpuinitdata = 0;
+
+static char Cx86_model[][9] __cpuinitdata = {
"Cx486", "Cx486", "5x86 ", "6x86", "MediaGX ", "6x86MX ",
"M II ", "Unknown"
};
-static char Cx486_name[][5] __initdata = {
+static char Cx486_name[][5] __cpuinitdata = {
"SLC", "DLC", "SLC2", "DLC2", "SRx", "DRx",
"SRx2", "DRx2"
};
-static char Cx486S_name[][4] __initdata = {
+static char Cx486S_name[][4] __cpuinitdata = {
"S", "S2", "Se", "S2e"
};
-static char Cx486D_name[][4] __initdata = {
+static char Cx486D_name[][4] __cpuinitdata = {
"DX", "DX2", "?", "?", "?", "DX4"
};
-static char Cx86_cb[] __initdata = "?.5x Core/Bus Clock";
-static char cyrix_model_mult1[] __initdata = "12??43";
-static char cyrix_model_mult2[] __initdata = "12233445";
+static char Cx86_cb[] __cpuinitdata = "?.5x Core/Bus Clock";
+static char cyrix_model_mult1[] __cpuinitdata = "12??43";
+static char cyrix_model_mult2[] __cpuinitdata = "12233445";
/*
* Reset the slow-loop (SLOP) bit on the 686(L) which is set by some old
@@ -82,7 +82,7 @@ static char cyrix_model_mult2[] __initda
extern void calibrate_delay(void) __init;
-static void __init check_cx686_slop(struct cpuinfo_x86 *c)
+static void __cpuinit check_cx686_slop(struct cpuinfo_x86 *c)
{
unsigned long flags;
@@ -107,7 +107,7 @@ static void __init check_cx686_slop(stru
}
-static void __init set_cx86_reorder(void)
+static void __cpuinit set_cx86_reorder(void)
{
u8 ccr3;
@@ -122,7 +122,7 @@ static void __init set_cx86_reorder(void
setCx86(CX86_CCR3, ccr3);
}
-static void __init set_cx86_memwb(void)
+static void __cpuinit set_cx86_memwb(void)
{
u32 cr0;
@@ -137,7 +137,7 @@ static void __init set_cx86_memwb(void)
setCx86(CX86_CCR2, getCx86(CX86_CCR2) | 0x14 );
}
-static void __init set_cx86_inc(void)
+static void __cpuinit set_cx86_inc(void)
{
unsigned char ccr3;
@@ -158,7 +158,7 @@ static void __init set_cx86_inc(void)
* Configure later MediaGX and/or Geode processor.
*/
-static void __init geode_configure(void)
+static void __cpuinit geode_configure(void)
{
unsigned long flags;
u8 ccr3, ccr4;
@@ -184,14 +184,14 @@ static void __init geode_configure(void)
#ifdef CONFIG_PCI
-static struct pci_device_id __initdata cyrix_55x0[] = {
+static struct pci_device_id __cpuinitdata cyrix_55x0[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5510) },
{ PCI_DEVICE(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5520) },
{ },
};
#endif
-static void __init init_cyrix(struct cpuinfo_x86 *c)
+static void __cpuinit init_cyrix(struct cpuinfo_x86 *c)
{
unsigned char dir0, dir0_msn, dir0_lsn, dir1 = 0;
char *buf = c->x86_model_id;
@@ -346,7 +346,7 @@ static void __init init_cyrix(struct cpu
/*
* Handle National Semiconductor branded processors
*/
-static void __init init_nsc(struct cpuinfo_x86 *c)
+static void __cpuinit init_nsc(struct cpuinfo_x86 *c)
{
/* There may be GX1 processors in the wild that are branded
* NSC and not Cyrix.
@@ -430,7 +430,7 @@ static void cyrix_identify(struct cpuinf
generic_identify(c);
}
-static struct cpu_dev cyrix_cpu_dev __initdata = {
+static struct cpu_dev cyrix_cpu_dev __cpuinitdata = {
.c_vendor = "Cyrix",
.c_ident = { "CyrixInstead" },
.c_init = init_cyrix,
@@ -443,17 +443,7 @@ int __init cyrix_init_cpu(void)
return 0;
}
-//early_arch_initcall(cyrix_init_cpu);
-
-static int __init cyrix_exit_cpu(void)
-{
- cpu_devs[X86_VENDOR_CYRIX] = NULL;
- return 0;
-}
-
-late_initcall(cyrix_exit_cpu);
-
-static struct cpu_dev nsc_cpu_dev __initdata = {
+static struct cpu_dev nsc_cpu_dev __cpuinitdata = {
.c_vendor = "NSC",
.c_ident = { "Geode by NSC" },
.c_init = init_nsc,
@@ -466,12 +456,3 @@ int __init nsc_init_cpu(void)
return 0;
}
-//early_arch_initcall(nsc_init_cpu);
-
-static int __init nsc_exit_cpu(void)
-{
- cpu_devs[X86_VENDOR_NSC] = NULL;
- return 0;
-}
-
-late_initcall(nsc_exit_cpu);
diff -r 55ec2b18fe7f -r 9010d63470ff arch/i386/kernel/cpu/intel.c
--- a/arch/i386/kernel/cpu/intel.c Thu Oct 09 15:23:54 2008 +0900
+++ b/arch/i386/kernel/cpu/intel.c Fri Oct 10 12:07:01 2008 +0900
@@ -198,7 +198,7 @@ static void __cpuinit init_intel(struct
}
-static unsigned int intel_size_cache(struct cpuinfo_x86 * c, unsigned int size)
+static unsigned int __cpuinit intel_size_cache(struct cpuinfo_x86 * c,
unsigned int size)
{
/* Intel PIII Tualatin. This comes in two flavours.
* One has 256kb of cache, the other 512. We have no way
diff -r 55ec2b18fe7f -r 9010d63470ff arch/i386/kernel/cpu/nexgen.c
--- a/arch/i386/kernel/cpu/nexgen.c Thu Oct 09 15:23:54 2008 +0900
+++ b/arch/i386/kernel/cpu/nexgen.c Fri Oct 10 12:07:01 2008 +0900
@@ -27,7 +27,7 @@ static int __init deep_magic_nexgen_prob
return ret;
}
-static void __init init_nexgen(struct cpuinfo_x86 * c)
+static void __cpuinit init_nexgen(struct cpuinfo_x86 * c)
{
c->x86_cache_size = 256; /* A few had 1 MB... */
}
@@ -41,7 +41,7 @@ static void __init nexgen_identify(struc
generic_identify(c);
}
-static struct cpu_dev nexgen_cpu_dev __initdata = {
+static struct cpu_dev nexgen_cpu_dev __cpuinitdata = {
.c_vendor = "Nexgen",
.c_ident = { "NexGenDriven" },
.c_models = {
@@ -59,13 +59,3 @@ int __init nexgen_init_cpu(void)
cpu_devs[X86_VENDOR_NEXGEN] = &nexgen_cpu_dev;
return 0;
}
-
-//early_arch_initcall(nexgen_init_cpu);
-
-static int __init nexgen_exit_cpu(void)
-{
- cpu_devs[X86_VENDOR_NEXGEN] = NULL;
- return 0;
-}
-
-late_initcall(nexgen_exit_cpu);
diff -r 55ec2b18fe7f -r 9010d63470ff arch/i386/kernel/cpu/rise.c
--- a/arch/i386/kernel/cpu/rise.c Thu Oct 09 15:23:54 2008 +0900
+++ b/arch/i386/kernel/cpu/rise.c Fri Oct 10 12:07:01 2008 +0900
@@ -5,7 +5,7 @@
#include "cpu.h"
-static void __init init_rise(struct cpuinfo_x86 *c)
+static void __cpuinit init_rise(struct cpuinfo_x86 *c)
{
printk("CPU: Rise iDragon");
if (c->x86_model > 2)
@@ -28,7 +28,7 @@ static void __init init_rise(struct cpui
set_bit(X86_FEATURE_CX8, c->x86_capability);
}
-static struct cpu_dev rise_cpu_dev __initdata = {
+static struct cpu_dev rise_cpu_dev __cpuinitdata = {
.c_vendor = "Rise",
.c_ident = { "RiseRiseRise" },
.c_models = {
@@ -50,12 +50,3 @@ int __init rise_init_cpu(void)
return 0;
}
-//early_arch_initcall(rise_init_cpu);
-
-static int __init rise_exit_cpu(void)
-{
- cpu_devs[X86_VENDOR_RISE] = NULL;
- return 0;
-}
-
-late_initcall(rise_exit_cpu);
diff -r 55ec2b18fe7f -r 9010d63470ff arch/i386/kernel/cpu/transmeta.c
--- a/arch/i386/kernel/cpu/transmeta.c Thu Oct 09 15:23:54 2008 +0900
+++ b/arch/i386/kernel/cpu/transmeta.c Fri Oct 10 12:07:01 2008 +0900
@@ -5,7 +5,7 @@
#include <asm/msr.h>
#include "cpu.h"
-static void __init init_transmeta(struct cpuinfo_x86 *c)
+static void __cpuinit init_transmeta(struct cpuinfo_x86 *c)
{
unsigned int cap_mask, uk, max, dummy;
unsigned int cms_rev1, cms_rev2;
@@ -98,7 +98,7 @@ static void __init transmeta_identify(st
}
}
-static struct cpu_dev transmeta_cpu_dev __initdata = {
+static struct cpu_dev transmeta_cpu_dev __cpuinitdata = {
.c_vendor = "Transmeta",
.c_ident = { "GenuineTMx86", "TransmetaCPU" },
.c_init = init_transmeta,
@@ -110,13 +110,3 @@ int __init transmeta_init_cpu(void)
cpu_devs[X86_VENDOR_TRANSMETA] = &transmeta_cpu_dev;
return 0;
}
-
-//early_arch_initcall(transmeta_init_cpu);
-
-static int __init transmeta_exit_cpu(void)
-{
- cpu_devs[X86_VENDOR_TRANSMETA] = NULL;
- return 0;
-}
-
-late_initcall(transmeta_exit_cpu);
diff -r 55ec2b18fe7f -r 9010d63470ff arch/i386/kernel/cpu/umc.c
--- a/arch/i386/kernel/cpu/umc.c Thu Oct 09 15:23:54 2008 +0900
+++ b/arch/i386/kernel/cpu/umc.c Fri Oct 10 12:07:01 2008 +0900
@@ -5,12 +5,8 @@
/* UMC chips appear to be only either 386 or 486, so no special init takes
place.
*/
-static void __init init_umc(struct cpuinfo_x86 * c)
-{
-}
-
-static struct cpu_dev umc_cpu_dev __initdata = {
+static struct cpu_dev umc_cpu_dev __cpuinitdata = {
.c_vendor = "UMC",
.c_ident = { "UMC UMC UMC" },
.c_models = {
@@ -21,7 +17,6 @@ static struct cpu_dev umc_cpu_dev __init
}
},
},
- .c_init = init_umc,
};
int __init umc_init_cpu(void)
@@ -29,13 +24,3 @@ int __init umc_init_cpu(void)
cpu_devs[X86_VENDOR_UMC] = &umc_cpu_dev;
return 0;
}
-
-//early_arch_initcall(umc_init_cpu);
-
-static int __init umc_exit_cpu(void)
-{
- cpu_devs[X86_VENDOR_UMC] = NULL;
- return 0;
-}
-
-late_initcall(umc_exit_cpu);
diff -r 55ec2b18fe7f -r 9010d63470ff arch/x86_64/mm/init-xen.c
--- a/arch/x86_64/mm/init-xen.c Thu Oct 09 15:23:54 2008 +0900
+++ b/arch/x86_64/mm/init-xen.c Fri Oct 10 12:07:01 2008 +0900
@@ -274,7 +274,7 @@ static __init void set_pte_phys(unsigned
new_pte = __pte(0);
pte = pte_offset_kernel(pmd, vaddr);
- if (!pte_none(*pte) &&
+ if (!pte_none(*pte) && pte_val(new_pte) &&
__pte_val(*pte) != (__pte_val(new_pte) & __supported_pte_mask))
pte_ERROR(*pte);
set_pte(pte, new_pte);
@@ -325,7 +325,7 @@ static __init void set_pte_phys_ma(unsig
new_pte = pfn_pte_ma(phys >> PAGE_SHIFT, prot);
pte = pte_offset_kernel(pmd, vaddr);
- if (!pte_none(*pte) &&
+ if (!pte_none(*pte) && pte_val(new_pte) &&
#ifdef CONFIG_ACPI
/* __acpi_map_table() fails to properly call clear_fixmap() */
(vaddr < __fix_to_virt(FIX_ACPI_END) ||
diff -r 55ec2b18fe7f -r 9010d63470ff drivers/pci/Makefile
--- a/drivers/pci/Makefile Thu Oct 09 15:23:54 2008 +0900
+++ b/drivers/pci/Makefile Fri Oct 10 12:07:01 2008 +0900
@@ -3,7 +3,8 @@
#
obj-y += access.o bus.o probe.o remove.o pci.o quirks.o \
- pci-driver.o search.o pci-sysfs.o rom.o setup-res.o
+ pci-driver.o search.o pci-sysfs.o rom.o setup-res.o \
+ reassigndev.o
obj-$(CONFIG_PROC_FS) += proc.o
# Build PCI Express stuff if needed
diff -r 55ec2b18fe7f -r 9010d63470ff drivers/pci/msi-xen.c
--- a/drivers/pci/msi-xen.c Thu Oct 09 15:23:54 2008 +0900
+++ b/drivers/pci/msi-xen.c Fri Oct 10 12:07:01 2008 +0900
@@ -67,7 +67,7 @@ static struct msi_dev_list *get_msi_dev_
}
/* Has not allocate msi_dev until now. */
- ret = kmalloc(sizeof(struct msi_dev_list), GFP_ATOMIC);
+ ret = kzalloc(sizeof(struct msi_dev_list), GFP_ATOMIC);
/* Failed to allocate msi_dev structure */
if ( !ret ) {
@@ -75,6 +75,7 @@ static struct msi_dev_list *get_msi_dev_
return NULL;
}
+ ret->dev = dev;
spin_lock_init(&ret->pirq_list_lock);
INIT_LIST_HEAD(&ret->pirq_list_head);
list_add_tail(&ret->list, &msi_dev_head);
diff -r 55ec2b18fe7f -r 9010d63470ff drivers/pci/pci.h
--- a/drivers/pci/pci.h Thu Oct 09 15:23:54 2008 +0900
+++ b/drivers/pci/pci.h Fri Oct 10 12:07:01 2008 +0900
@@ -99,3 +99,8 @@ pci_match_one_device(const struct pci_de
return NULL;
}
+#define ROUND_UP_TO_PAGESIZE(size) ((size + PAGE_SIZE - 1) & ~(PAGE_SIZE - 1))
+
+extern int reassign_resources;
+extern int is_reassigndev(struct pci_dev *dev);
+extern void pci_update_bridge(struct pci_dev *dev, int resno);
diff -r 55ec2b18fe7f -r 9010d63470ff drivers/pci/quirks.c
--- a/drivers/pci/quirks.c Thu Oct 09 15:23:54 2008 +0900
+++ b/drivers/pci/quirks.c Fri Oct 10 12:07:01 2008 +0900
@@ -33,6 +33,19 @@ static int __init set_pci_mem_align(char
}
__setup("pci-mem-align", set_pci_mem_align);
+
+int reassign_resources = 0;
+
+static int __init set_reassign_resources(char *str)
+{
+ /* resources reassign on */
+ reassign_resources = 1;
+ printk(KERN_DEBUG "PCI: resource reassign ON.\n");
+
+ return 1;
+}
+__setup("reassign_resources", set_reassign_resources);
+
/* This quirk function enables us to force all memory resources which are
* assigned to PCI devices, to be page-aligned.
*/
@@ -41,6 +54,42 @@ static void __devinit quirk_align_mem_re
int i;
struct resource *r;
resource_size_t old_start;
+
+ if (reassign_resources) {
+ if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
+ (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
+ /* PCI Host Bridge isn't a target device */
+ return;
+ }
+ if (is_reassigndev(dev)) {
+ printk(KERN_INFO
+ "PCI: Disable device and release resources"
+ " [%s].\n", pci_name(dev));
+ pci_disable_device(dev);
+
+ for (i=0; i < PCI_NUM_RESOURCES; i++) {
+ r = &dev->resource[i];
+ if ((r == NULL) ||
+ !(r->flags & IORESOURCE_MEM))
+ continue;
+
+ r->end = r->end - r->start;
+ r->start = 0;
+
+ if (i < PCI_BRIDGE_RESOURCES) {
+ pci_update_resource(dev, r, i);
+ } else if (i == 8 || i == 9) {
+ /* need to update(clear) the Base/Limit
+ * register also, because PCI bridge is
+ * disabled and the resource is
+ * released.
+ */
+ pci_update_bridge(dev, i);
+ }
+ }
+ }
+ return;
+ }
if (!pci_mem_align)
return;
diff -r 55ec2b18fe7f -r 9010d63470ff drivers/pci/reassigndev.c
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/drivers/pci/reassigndev.c Fri Oct 10 12:07:01 2008 +0900
@@ -0,0 +1,80 @@
+/*
+ * Copyright (c) 2008, NEC Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
+ * Place - Suite 330, Boston, MA 02111-1307 USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/string.h>
+#include "pci.h"
+
+
+#define REASSIGNDEV_PARAM_MAX (2048)
+#define TOKEN_MAX (12) /* "SSSS:BB:DD.F" length is 12 */
+
+static char param_reassigndev[REASSIGNDEV_PARAM_MAX] = {0};
+
+static int __init reassigndev_setup(char *str)
+{
+ strncpy(param_reassigndev, str, REASSIGNDEV_PARAM_MAX);
+ param_reassigndev[REASSIGNDEV_PARAM_MAX - 1] = '\0';
+ return 1;
+}
+__setup("reassigndev=", reassigndev_setup);
+
+int is_reassigndev(struct pci_dev *dev)
+{
+ char dev_str[TOKEN_MAX+1];
+ int seg, bus, slot, func;
+ int len;
+ char *p, *next_str;
+
+ p = param_reassigndev;
+ for (; p; p = next_str + 1) {
+ next_str = strpbrk(p, ",");
+ if (next_str) {
+ len = next_str - p;
+ } else {
+ len = strlen(p);
+ }
+ if (len > 0 && len <= TOKEN_MAX) {
+ strncpy(dev_str, p, len);
+ *(dev_str + len) = '\0';
+
+ if (sscanf(dev_str, "%x:%x:%x.%x",
+ &seg, &bus, &slot, &func) != 4) {
+ if (sscanf(dev_str, "%x:%x.%x",
+ &bus, &slot, &func) == 3) {
+ seg = 0;
+ } else {
+ /* failed to scan strings */
+ seg = -1;
+ bus = -1;
+ }
+ }
+ if (seg == pci_domain_nr(dev->bus) &&
+ bus == dev->bus->number &&
+ slot == PCI_SLOT(dev->devfn) &&
+ func == PCI_FUNC(dev->devfn)) {
+ /* It's a target device */
+ return 1;
+ }
+ }
+ if (!next_str)
+ break;
+ }
+
+ return 0;
+}
diff -r 55ec2b18fe7f -r 9010d63470ff drivers/pci/setup-bus.c
--- a/drivers/pci/setup-bus.c Thu Oct 09 15:23:54 2008 +0900
+++ b/drivers/pci/setup-bus.c Fri Oct 10 12:07:01 2008 +0900
@@ -26,6 +26,7 @@
#include <linux/cache.h>
#include <linux/slab.h>
+#include "pci.h"
#define DEBUG_CONFIG 1
#if DEBUG_CONFIG
@@ -344,7 +345,8 @@ pbus_size_mem(struct pci_bus *bus, unsig
list_for_each_entry(dev, &bus->devices, bus_list) {
int i;
-
+ int reassign = reassign_resources ? is_reassigndev(dev) : 0;
+
for (i = 0; i < PCI_NUM_RESOURCES; i++) {
struct resource *r = &dev->resource[i];
unsigned long r_size;
@@ -352,6 +354,11 @@ pbus_size_mem(struct pci_bus *bus, unsig
if (r->parent || (r->flags & mask) != type)
continue;
r_size = r->end - r->start + 1;
+
+ if (reassign) {
+ r_size = ROUND_UP_TO_PAGESIZE(r_size);
+ }
+
/* For bridges size != alignment */
align = (i < PCI_BRIDGE_RESOURCES) ? r_size : r->start;
order = __ffs(align) - 20;
diff -r 55ec2b18fe7f -r 9010d63470ff drivers/pci/setup-res.c
--- a/drivers/pci/setup-res.c Thu Oct 09 15:23:54 2008 +0900
+++ b/drivers/pci/setup-res.c Fri Oct 10 12:07:01 2008 +0900
@@ -117,19 +117,96 @@ pci_claim_resource(struct pci_dev *dev,
}
EXPORT_SYMBOL_GPL(pci_claim_resource);
+void
+pci_update_bridge(struct pci_dev *dev, int resno)
+{
+ struct resource *res = &dev->resource[resno];
+ struct pci_bus_region region;
+ u32 l, dw, base_up32, limit_up32;
+
+ if (dev->hdr_type != PCI_HEADER_TYPE_BRIDGE ||
+ (dev->class >> 8) != PCI_CLASS_BRIDGE_PCI) {
+ return;
+ }
+
+ if (!res->flags)
+ return;
+
+ switch (resno) {
+ case 8 : /* MMIO Base/Limit */
+ pcibios_resource_to_bus(dev, ®ion, res);
+ if (res->flags & IORESOURCE_MEM &&
+ !(res->flags & IORESOURCE_PREFETCH)) {
+ l = (region.start >> 16) & 0xfff0;
+ l |= region.end & 0xfff00000;
+ } else {
+ l = 0x0000fff0;
+ }
+ pci_write_config_dword(dev, PCI_MEMORY_BASE, l);
+
+ break;
+
+ case 9 : /* Prefetchable MMIO Base/Limit */
+ /* Clear out the upper 32 bits of PREF limit.
+ * If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily
+ * disables PREF range, which is ok.
+ */
+ pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, 0);
+
+ /* Get PREF 32/64 bits Addressing mode */
+ pci_read_config_dword(dev, PCI_PREF_MEMORY_BASE, &dw);
+
+ pcibios_resource_to_bus(dev, ®ion, res);
+ if (res->flags & IORESOURCE_MEM &&
+ res->flags & IORESOURCE_PREFETCH) {
+ l = (region.start >> 16) & 0xfff0;
+ l |= region.end & 0xfff00000;
+
+ if (dw & PCI_PREF_RANGE_TYPE_64) {
+ base_up32 = (region.start >> 32) & 0xffffffff;
+ limit_up32 = (region.end >> 32) & 0xffffffff;
+ } else {
+ base_up32 = 0;
+ limit_up32 = 0;
+ }
+ } else {
+ l = 0x0000fff0;
+ base_up32 = 0xffffffff;
+ limit_up32 = 0;
+ }
+ pci_write_config_dword(dev, PCI_PREF_MEMORY_BASE, l);
+ /* Set up the upper 32 bits of PREF base/limit. */
+ pci_write_config_dword(dev, PCI_PREF_BASE_UPPER32, base_up32);
+ pci_write_config_dword(dev, PCI_PREF_LIMIT_UPPER32, limit_up32);
+ break;
+ default :
+ BUG();
+ break;
+ }
+}
+
int pci_assign_resource(struct pci_dev *dev, int resno)
{
struct pci_bus *bus = dev->bus;
struct resource *res = dev->resource + resno;
resource_size_t size, min, align;
int ret;
+ int reassigndev = reassign_resources ? is_reassigndev(dev) : 0;
size = res->end - res->start + 1;
min = (res->flags & IORESOURCE_IO) ? PCIBIOS_MIN_IO : PCIBIOS_MIN_MEM;
/* The bridge resources are special, as their
size != alignment. Sizing routines return
required alignment in the "start" field. */
- align = (resno < PCI_BRIDGE_RESOURCES) ? size : res->start;
+ if (resno < PCI_BRIDGE_RESOURCES) {
+ align = size;
+ if ((reassigndev) &&
+ (res->flags & IORESOURCE_MEM)) {
+ align = ROUND_UP_TO_PAGESIZE(align);
+ }
+ } else {
+ align = res->start;
+ }
/* First, try exact prefetching match.. */
ret = pci_bus_alloc_resource(bus, res, size, align, min,
@@ -154,6 +231,9 @@ int pci_assign_resource(struct pci_dev *
resno, (unsigned long long)size,
(unsigned long long)res->start, pci_name(dev));
} else if (resno < PCI_BRIDGE_RESOURCES) {
+ printk(KERN_DEBUG "PCI: Assign resource(%d) on %s "
+ "%016llx - %016llx\n", resno, pci_name(dev),
+ (u64)res->start, (u64)res->end);
pci_update_resource(dev, res, resno);
}
diff -r 55ec2b18fe7f -r 9010d63470ff drivers/xen/core/evtchn.c
--- a/drivers/xen/core/evtchn.c Thu Oct 09 15:23:54 2008 +0900
+++ b/drivers/xen/core/evtchn.c Fri Oct 10 12:07:01 2008 +0900
@@ -756,7 +756,16 @@ static struct hw_interrupt_type dynirq_t
void evtchn_register_pirq(int irq)
{
+ struct irq_desc *desc;
+ unsigned long flags;
+
irq_info[irq] = mk_irq_info(IRQT_PIRQ, irq, 0);
+
+ /* Cannot call set_irq_probe(), as that's marked __init. */
+ desc = irq_desc + irq;
+ spin_lock_irqsave(&desc->lock, flags);
+ desc->status &= ~IRQ_NOPROBE;
+ spin_unlock_irqrestore(&desc->lock, flags);
}
#if defined(CONFIG_X86_IO_APIC)
@@ -1105,7 +1114,7 @@ void __init xen_init_IRQ(void)
for (i = DYNIRQ_BASE; i < (DYNIRQ_BASE + NR_DYNIRQS); i++) {
irq_bindcount[i] = 0;
- irq_desc[i].status = IRQ_DISABLED;
+ irq_desc[i].status = IRQ_DISABLED|IRQ_NOPROBE;
irq_desc[i].action = NULL;
irq_desc[i].depth = 1;
irq_desc[i].chip = &dynirq_type;
@@ -1123,6 +1132,8 @@ void __init xen_init_IRQ(void)
#endif
irq_desc[i].status = IRQ_DISABLED;
+ if (!identity_mapped_irq(i))
+ irq_desc[i].status |= IRQ_NOPROBE;
irq_desc[i].action = NULL;
irq_desc[i].depth = 1;
irq_desc[i].chip = &pirq_type;
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