# HG changeset patch
# User Keir Fraser <keir.fraser@xxxxxxxxxx>
# Date 1221489878 -3600
# Node ID 75c4a603d9cd7f73366986261e1078fce1ead815
# Parent 59aba2cbbb58111de1aba6b173800d62956cf26f
x86: Fix 32-bit build after AMD microcode update patch.
Signed-off-by: Keir Fraser <keir.fraser@xxxxxxxxxx>
---
xen/arch/x86/microcode_amd.c | 9 ++++-----
1 files changed, 4 insertions(+), 5 deletions(-)
diff -r 59aba2cbbb58 -r 75c4a603d9cd xen/arch/x86/microcode_amd.c
--- a/xen/arch/x86/microcode_amd.c Mon Sep 15 11:36:20 2008 +0100
+++ b/xen/arch/x86/microcode_amd.c Mon Sep 15 15:44:38 2008 +0100
@@ -170,11 +170,10 @@ static int apply_microcode_amd(int cpu)
static int apply_microcode_amd(int cpu)
{
unsigned long flags;
- unsigned int eax, edx;
- unsigned int rev;
+ uint32_t eax, edx, rev;
int cpu_num = raw_smp_processor_id();
struct ucode_cpu_info *uci = ucode_cpu_info + cpu_num;
- unsigned long addr;
+ uint64_t addr;
/* We should bind the task to the CPU */
BUG_ON(cpu_num != cpu);
@@ -185,8 +184,8 @@ static int apply_microcode_amd(int cpu)
spin_lock_irqsave(µcode_update_lock, flags);
addr = (unsigned long)&uci->mc.mc_amd->hdr.data_code;
- edx = (unsigned int)((unsigned long)(addr >> 32));
- eax = (unsigned int)((unsigned long)(addr & 0xffffffff));
+ edx = (uint32_t)(addr >> 32);
+ eax = (uint32_t)addr;
asm volatile("movl %0, %%ecx; wrmsr" :
: "i" (MSR_AMD_PATCHLOADER), "a" (eax), "d" (edx) : "ecx");
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