[Xen-changelog] [xen-unstable] [IA64] Improve priv_emulate() isr.code handling for IA64_GENEX_VECTOR

[Xen patchbot-unstable <patchbot-unstable@xxxxxxxxxxxxxxxxxxx>]

# HG changeset patch
# User Alex Williamson <alex.williamson@xxxxxx>
# Date 1182195691 21600
# Node ID 0944634d463906941e985e936ebea4dcf87445f0
# Parent  bdcb9cf6073d180fa64f7213b59540194e4031f8
[IA64] Improve priv_emulate() isr.code handling for IA64_GENEX_VECTOR

Better handling of isr.code if priv_emulate() fails with IA64_GENEX_VECTOR.

Signed-off-by: Dietmar Hahn <dietmar.hahn@xxxxxxxxxxxxxxxxxxx>
---
 xen/arch/ia64/xen/faults.c |    8 ++++++++
 1 files changed, 8 insertions(+)

diff -r bdcb9cf6073d -r 0944634d4639 xen/arch/ia64/xen/faults.c
--- a/xen/arch/ia64/xen/faults.c        Mon Jun 18 13:36:36 2007 -0600
+++ b/xen/arch/ia64/xen/faults.c        Mon Jun 18 13:41:31 2007 -0600
@@ -544,6 +544,14 @@ ia64_handle_privop(unsigned long ifa, st
        if (vector != IA64_NO_FAULT && vector != IA64_RFI_IN_PROGRESS) {
                // Note: if a path results in a vector to reflect that requires
                // iha/itir (e.g. vcpu_force_data_miss), they must be set there
+               /*
+                * IA64_GENEX_VECTOR may contain in the lowest byte an ISR.code
+                * see IA64_ILLOP_FAULT, ...
+                */
+               if ((vector & ~0xffUL) == IA64_GENEX_VECTOR) {
+                       isr = vector & 0xffUL;
+                       vector = IA64_GENEX_VECTOR;
+               }
                reflect_interruption(isr, regs, vector);
        }
 }

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