# HG changeset patch
# User awilliam@xxxxxxxxxxx
# Node ID f6007621cc0c0e4d44050e356f228cd7be483c47
# Parent 3470d9cd27e5caf555b3df6e1b29ae4f3f96c3ac
[IA64] VTi TLB miss fix
When present bit is 0, inject page not present fault to guest.
Signed-off-by: Anthony Xu <anthony.xu@xxxxxxxxx>
---
xen/arch/ia64/vmx/vmmu.c | 13 +----
xen/arch/ia64/vmx/vmx_interrupt.c | 19 +++++++-
xen/arch/ia64/vmx/vmx_process.c | 88 +++++++++++++++-----------------------
xen/include/asm-ia64/vmx_vcpu.h | 3 -
4 files changed, 58 insertions(+), 65 deletions(-)
diff -r 3470d9cd27e5 -r f6007621cc0c xen/arch/ia64/vmx/vmmu.c
--- a/xen/arch/ia64/vmx/vmmu.c Sun Oct 01 10:48:40 2006 -0600
+++ b/xen/arch/ia64/vmx/vmmu.c Sun Oct 01 11:05:24 2006 -0600
@@ -645,37 +645,30 @@ IA64FAULT vmx_vcpu_tpa(VCPU *vcpu, UINT6
visr.ei=pt_isr.ei;
visr.ir=pt_isr.ir;
vpsr.val = VCPU(vcpu, vpsr);
- if(vpsr.ic==0){
- visr.ni=1;
- }
visr.na=1;
data = vtlb_lookup(vcpu, vadr, DSIDE_TLB);
if(data){
if(data->p==0){
- visr.na=1;
vcpu_set_isr(vcpu,visr.val);
- page_not_present(vcpu, vadr);
+ data_page_not_present(vcpu, vadr);
return IA64_FAULT;
}else if(data->ma == VA_MATTR_NATPAGE){
- visr.na = 1;
vcpu_set_isr(vcpu, visr.val);
dnat_page_consumption(vcpu, vadr);
return IA64_FAULT;
}else{
*padr = ((data->ppn >> (data->ps - 12)) << data->ps) |
- (vadr & (PSIZE(data->ps) - 1));
+ (vadr & (PSIZE(data->ps) - 1));
return IA64_NO_FAULT;
}
}
data = vhpt_lookup(vadr);
if(data){
if(data->p==0){
- visr.na=1;
vcpu_set_isr(vcpu,visr.val);
- page_not_present(vcpu, vadr);
+ data_page_not_present(vcpu, vadr);
return IA64_FAULT;
}else if(data->ma == VA_MATTR_NATPAGE){
- visr.na = 1;
vcpu_set_isr(vcpu, visr.val);
dnat_page_consumption(vcpu, vadr);
return IA64_FAULT;
diff -r 3470d9cd27e5 -r f6007621cc0c xen/arch/ia64/vmx/vmx_interrupt.c
--- a/xen/arch/ia64/vmx/vmx_interrupt.c Sun Oct 01 10:48:40 2006 -0600
+++ b/xen/arch/ia64/vmx/vmx_interrupt.c Sun Oct 01 11:05:24 2006 -0600
@@ -383,14 +383,29 @@ dnat_page_consumption (VCPU *vcpu, uint6
/* Deal with
* Page not present vector
*/
-void
-page_not_present(VCPU *vcpu, u64 vadr)
+static void
+__page_not_present(VCPU *vcpu, u64 vadr)
{
/* If vPSR.ic, IFA, ITIR */
set_ifa_itir_iha (vcpu, vadr, 1, 1, 0);
inject_guest_interruption(vcpu, IA64_PAGE_NOT_PRESENT_VECTOR);
}
+
+void
+data_page_not_present(VCPU *vcpu, u64 vadr)
+{
+ __page_not_present(vcpu, vadr);
+}
+
+
+void
+inst_page_not_present(VCPU *vcpu, u64 vadr)
+{
+ __page_not_present(vcpu, vadr);
+}
+
+
/* Deal with
* Data access rights vector
*/
diff -r 3470d9cd27e5 -r f6007621cc0c xen/arch/ia64/vmx/vmx_process.c
--- a/xen/arch/ia64/vmx/vmx_process.c Sun Oct 01 10:48:40 2006 -0600
+++ b/xen/arch/ia64/vmx/vmx_process.c Sun Oct 01 11:05:24 2006 -0600
@@ -263,18 +263,20 @@ vmx_hpw_miss(u64 vadr , u64 vec, REGS* r
vmx_hpw_miss(u64 vadr , u64 vec, REGS* regs)
{
IA64_PSR vpsr;
- int type=ISIDE_TLB;
+ int type;
u64 vhpt_adr, gppa, pteval, rr, itir;
ISR misr;
-// REGS *regs;
thash_data_t *data;
VCPU *v = current;
-#ifdef VTLB_DEBUG
- check_vtlb_sanity(vtlb);
- dump_vtlb(vtlb);
-#endif
vpsr.val = VCPU(v, vpsr);
misr.val=VMX(v,cr_isr);
+
+ if (vec == 1)
+ type = ISIDE_TLB;
+ else if (vec == 2)
+ type = DSIDE_TLB;
+ else
+ panic_domain(regs, "wrong vec:%lx\n", vec);
if(is_physical_mode(v)&&(!(vadr<<1>>62))){
if(vec==2){
@@ -286,11 +288,6 @@ vmx_hpw_miss(u64 vadr , u64 vec, REGS* r
physical_tlb_miss(v, vadr);
return IA64_FAULT;
}
- if(vec == 1) type = ISIDE_TLB;
- else if(vec == 2) type = DSIDE_TLB;
- else panic_domain(regs,"wrong vec:%lx\n",vec);
-
-// prepare_if_physical_mode(v);
if((data=vtlb_lookup(v, vadr,type))!=0){
if (v->domain != dom0 && type == DSIDE_TLB) {
@@ -309,46 +306,44 @@ vmx_hpw_miss(u64 vadr , u64 vec, REGS* r
thash_vhpt_insert(v,data->page_flags, data->itir ,vadr);
}else if(type == DSIDE_TLB){
+
if (misr.sp)
return vmx_handle_lds(regs);
+
if(!vhpt_enabled(v, vadr, misr.rs?RSE_REF:DATA_REF)){
if(vpsr.ic){
vcpu_set_isr(v, misr.val);
alt_dtlb(v, vadr);
return IA64_FAULT;
} else{
- if(misr.sp){
- //TODO lds emulation
- //panic("Don't support speculation load");
- return vmx_handle_lds(regs);
- }else{
- nested_dtlb(v);
- return IA64_FAULT;
- }
+ nested_dtlb(v);
+ return IA64_FAULT;
}
} else{
vmx_vcpu_thash(v, vadr, &vhpt_adr);
if(!guest_vhpt_lookup(vhpt_adr, &pteval)){
- if ((pteval & _PAGE_P) &&
- ((pteval & _PAGE_MA_MASK) != _PAGE_MA_ST)) {
+ if (!(pteval & _PAGE_P)) {
+ if (vpsr.ic) {
+ vcpu_set_isr(v, misr.val);
+ data_page_not_present(v, vadr);
+ return IA64_FAULT;
+ } else {
+ nested_dtlb(v);
+ return IA64_FAULT;
+ }
+ }
+ else if ((pteval & _PAGE_MA_MASK) != _PAGE_MA_ST) {
vcpu_get_rr(v, vadr, &rr);
itir = rr&(RR_RID_MASK | RR_PS_MASK);
thash_purge_and_insert(v, pteval, itir, vadr, DSIDE_TLB);
return IA64_NO_FAULT;
- }
- if(vpsr.ic){
+ } else if (vpsr.ic) {
vcpu_set_isr(v, misr.val);
dtlb_fault(v, vadr);
return IA64_FAULT;
}else{
- if(misr.sp){
- //TODO lds emulation
- //panic("Don't support speculation load");
- return vmx_handle_lds(regs);
- }else{
- nested_dtlb(v);
- return IA64_FAULT;
- }
+ nested_dtlb(v);
+ return IA64_FAULT;
}
}else{
if(vpsr.ic){
@@ -356,22 +351,16 @@ vmx_hpw_miss(u64 vadr , u64 vec, REGS* r
dvhpt_fault(v, vadr);
return IA64_FAULT;
}else{
- if(misr.sp){
- //TODO lds emulation
- //panic("Don't support speculation load");
- return vmx_handle_lds(regs);
- }else{
- nested_dtlb(v);
- return IA64_FAULT;
- }
+ nested_dtlb(v);
+ return IA64_FAULT;
}
}
}
}else if(type == ISIDE_TLB){
+
+ if (!vpsr.ic)
+ misr.ni = 1;
if(!vhpt_enabled(v, vadr, misr.rs?RSE_REF:DATA_REF)){
- if(!vpsr.ic){
- misr.ni=1;
- }
vcpu_set_isr(v, misr.val);
alt_itlb(v, vadr);
return IA64_FAULT;
@@ -383,17 +372,12 @@ vmx_hpw_miss(u64 vadr , u64 vec, REGS* r
itir = rr&(RR_RID_MASK | RR_PS_MASK);
thash_purge_and_insert(v, pteval, itir, vadr, ISIDE_TLB);
return IA64_NO_FAULT;
- }
- if(!vpsr.ic){
- misr.ni=1;
- }
- vcpu_set_isr(v, misr.val);
- itlb_fault(v, vadr);
- return IA64_FAULT;
+ } else {
+ vcpu_set_isr(v, misr.val);
+ inst_page_not_present(v, vadr);
+ return IA64_FAULT;
+ }
}else{
- if(!vpsr.ic){
- misr.ni=1;
- }
vcpu_set_isr(v, misr.val);
ivhpt_fault(v, vadr);
return IA64_FAULT;
diff -r 3470d9cd27e5 -r f6007621cc0c xen/include/asm-ia64/vmx_vcpu.h
--- a/xen/include/asm-ia64/vmx_vcpu.h Sun Oct 01 10:48:40 2006 -0600
+++ b/xen/include/asm-ia64/vmx_vcpu.h Sun Oct 01 11:05:24 2006 -0600
@@ -122,7 +122,8 @@ extern void alt_dtlb (VCPU *vcpu, u64 va
extern void alt_dtlb (VCPU *vcpu, u64 vadr);
extern void dvhpt_fault (VCPU *vcpu, u64 vadr);
extern void dnat_page_consumption (VCPU *vcpu, uint64_t vadr);
-extern void page_not_present(VCPU *vcpu, u64 vadr);
+extern void data_page_not_present(VCPU *vcpu, u64 vadr);
+extern void inst_page_not_present(VCPU *vcpu, u64 vadr);
extern void data_access_rights(VCPU *vcpu, u64 vadr);
/**************************************************************************
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