# HG changeset patch
# User kaf24@xxxxxxxxxxxxxxxxxxxx
# Date 1159611114 -3600
# Node ID 96a6649fa691b78fcc6af0bb6618940982d72537
# Parent 2d155d41fe466952c8b9b871b4500b7f7a29f088
[HVM] Add RDMSR/WRMSR instruction emulation to VMXAssist decoder
AP of PAE SMP windows will use it to set NX bit in EFER.
Signed-off-by: Xin Li <xin.b.li@xxxxxxxxx>
---
tools/firmware/vmxassist/vm86.c | 18 ++++++++++++++++++
1 files changed, 18 insertions(+)
diff -r 2d155d41fe46 -r 96a6649fa691 tools/firmware/vmxassist/vm86.c
--- a/tools/firmware/vmxassist/vm86.c Sat Sep 30 11:08:41 2006 +0100
+++ b/tools/firmware/vmxassist/vm86.c Sat Sep 30 11:11:54 2006 +0100
@@ -1230,6 +1230,18 @@ pushrm(struct regs *regs, int prefix, un
enum { OPC_INVALID, OPC_EMULATED };
+#define rdmsr(msr,val1,val2) \
+ __asm__ __volatile__( \
+ "rdmsr" \
+ : "=a" (val1), "=d" (val2) \
+ : "c" (msr))
+
+#define wrmsr(msr,val1,val2) \
+ __asm__ __volatile__( \
+ "wrmsr" \
+ : /* no outputs */ \
+ : "c" (msr), "a" (val1), "d" (val2))
+
/*
* Emulate a single instruction, including all its prefixes. We only implement
* a small subset of the opcodes, and not all opcodes are implemented for each
@@ -1288,6 +1300,12 @@ opcode(struct regs *regs)
if (!movcr(regs, prefix, opc))
goto invalid;
return OPC_EMULATED;
+ case 0x30: /* WRMSR */
+ wrmsr(regs->ecx, regs->eax, regs->edx);
+ return OPC_EMULATED;
+ case 0x32: /* RDMSR */
+ rdmsr(regs->ecx, regs->eax, regs->edx);
+ return OPC_EMULATED;
default:
goto invalid;
}
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