# HG changeset patch
# User emellor@xxxxxxxxxxxxxxxxxxxxxx
# Node ID 237b2a4d2499fbb3c9105677afb36be1c36741f5
# Parent d8c7f144ca5425f493447a8bdfab668c64feb5e9
# Parent dc8122d906702a682dc896de44a32b7d27794586
Merged.
diff -r d8c7f144ca54 -r 237b2a4d2499
linux-2.6-xen-sparse/drivers/xen/console/console.c
--- a/linux-2.6-xen-sparse/drivers/xen/console/console.c Thu Dec 15
13:49:07 2005
+++ b/linux-2.6-xen-sparse/drivers/xen/console/console.c Thu Dec 15
13:49:19 2005
@@ -628,6 +628,7 @@
if (xencons_driver == NULL)
return -ENOMEM;
+ DRV(xencons_driver)->name = "xencons";
DRV(xencons_driver)->major = TTY_MAJOR;
DRV(xencons_driver)->type = TTY_DRIVER_TYPE_SERIAL;
DRV(xencons_driver)->subtype = SERIAL_TYPE_NORMAL;
diff -r d8c7f144ca54 -r 237b2a4d2499 xen/arch/ia64/vmx/vlsapic.c
--- a/xen/arch/ia64/vmx/vlsapic.c Thu Dec 15 13:49:07 2005
+++ b/xen/arch/ia64/vmx/vlsapic.c Thu Dec 15 13:49:19 2005
@@ -476,19 +476,20 @@
* May come from virtualization fault or
* nested host interrupt.
*/
-void vmx_vcpu_pend_interrupt(VCPU *vcpu, UINT64 vector)
+int vmx_vcpu_pend_interrupt(VCPU *vcpu, uint8_t vector)
{
uint64_t spsr;
+ int ret;
if (vector & ~0xff) {
DPRINTK("vmx_vcpu_pend_interrupt: bad vector\n");
return;
}
local_irq_save(spsr);
- VCPU(vcpu,irr[vector>>6]) |= 1UL<<(vector&63);
- //vlapic_update_shared_irr(vcpu);
+ ret = test_and_set_bit(vector, &VCPU(vcpu, irr[0]));
local_irq_restore(spsr);
vcpu->arch.irq_new_pending = 1;
+ return ret;
}
/*
@@ -505,7 +506,6 @@
for (i=0 ; i<4; i++ ) {
VCPU(vcpu,irr[i]) |= pend_irr[i];
}
- //vlapic_update_shared_irr(vcpu);
local_irq_restore(spsr);
vcpu->arch.irq_new_pending = 1;
}
@@ -592,7 +592,6 @@
VLSAPIC_INSVC(vcpu,vec>>6) |= (1UL <<(vec&63));
VCPU(vcpu, irr[vec>>6]) &= ~(1UL <<(vec&63));
update_vhpi(vcpu, NULL_VECTOR); // clear VHPI till EOI or IRR write
- //vlapic_update_shared_irr(vcpu);
local_irq_restore(spsr);
return (uint64_t)vec;
}
diff -r d8c7f144ca54 -r 237b2a4d2499 xen/arch/x86/dm/vmx_vioapic.c
--- a/xen/arch/x86/dm/vmx_vioapic.c Thu Dec 15 13:49:07 2005
+++ b/xen/arch/x86/dm/vmx_vioapic.c Thu Dec 15 13:49:19 2005
@@ -306,14 +306,8 @@
switch (delivery_mode) {
case VLAPIC_DELIV_MODE_FIXED:
case VLAPIC_DELIV_MODE_LPRI:
- if (test_and_set_bit(vector, &VLAPIC_IRR(target)) && trig_mode == 1) {
- /* the level interrupt should not happen before it is cleard */
+ if (vlapic_set_irq(target, vector, trig_mode) && (trig_mode == 1))
printk("<ioapic_inj_irq> level interrupt happen before cleard\n");
- }
-#ifndef __ia64__
- if (trig_mode)
- test_and_set_bit(vector, &target->tmr[0]);
-#endif
result = 1;
break;
default:
diff -r d8c7f144ca54 -r 237b2a4d2499 xen/arch/x86/vmx.c
--- a/xen/arch/x86/vmx.c Thu Dec 15 13:49:07 2005
+++ b/xen/arch/x86/vmx.c Thu Dec 15 13:49:19 2005
@@ -503,6 +503,8 @@
__vm_clear_bit(EXCEPTION_BITMAP, EXCEPTION_BITMAP_NM);
}
+/* Reserved bits: [31:15], [12:11], [9], [6], [2:1] */
+#define VMX_VCPU_CPUID_L1_RESERVED 0xffff9a46
static void vmx_vmexit_do_cpuid(unsigned long input, struct cpu_user_regs
*regs)
{
@@ -537,6 +539,7 @@
}
/* Unsupportable for virtualised CPUs. */
+ ecx &= ~VMX_VCPU_CPUID_L1_RESERVED; /* mask off reserved bits */
clear_bit(X86_FEATURE_VMXE & 31, &ecx);
clear_bit(X86_FEATURE_MWAIT & 31, &ecx);
}
@@ -1091,11 +1094,21 @@
unsigned long eip;
int paging_enabled;
unsigned long vm_entry_value;
+ unsigned long old_cr0;
/*
* CR0: We don't want to lose PE and PG.
*/
- paging_enabled = vmx_paging_enabled(v);
+ __vmread_vcpu(v, CR0_READ_SHADOW, &old_cr0);
+ paging_enabled = (old_cr0 & X86_CR0_PE) && (old_cr0 & X86_CR0_PG);
+ /* If OS don't use clts to clear TS bit...*/
+ if((old_cr0 & X86_CR0_TS) && !(value & X86_CR0_TS))
+ {
+ clts();
+ setup_fpu(v);
+ }
+
+
__vmwrite(GUEST_CR0, value | X86_CR0_PE | X86_CR0_PG | X86_CR0_NE);
__vmwrite(CR0_READ_SHADOW, value);
diff -r d8c7f144ca54 -r 237b2a4d2499 xen/include/asm-ia64/vmx_platform.h
--- a/xen/include/asm-ia64/vmx_platform.h Thu Dec 15 13:49:07 2005
+++ b/xen/include/asm-ia64/vmx_platform.h Thu Dec 15 13:49:19 2005
@@ -55,6 +55,12 @@
#define VLAPIC_ID(l) (uint16_t)(VCPU((l)->vcpu, lid) >> 16)
#define VLAPIC_IRR(l) VCPU((l)->vcpu, irr[0])
+extern int vmx_vcpu_pend_interrupt(struct vcpu *vcpu, uint8_t vector);
+static inline int vlapic_set_irq(struct vlapic *t, uint8_t vec, uint8_t trig)
+{
+ return vmx_vcpu_pend_interrupt(t->vcpu, vec);
+}
+
/* As long as we register vlsapic to ioapic controller, it's said enabled */
#define vlapic_enabled(l) 1
#define vmx_apic_support(d) 1
diff -r d8c7f144ca54 -r 237b2a4d2499 xen/include/asm-ia64/vmx_vcpu.h
--- a/xen/include/asm-ia64/vmx_vcpu.h Thu Dec 15 13:49:07 2005
+++ b/xen/include/asm-ia64/vmx_vcpu.h Thu Dec 15 13:49:19 2005
@@ -112,7 +112,7 @@
extern void guest_write_eoi(VCPU *vcpu);
extern uint64_t guest_read_vivr(VCPU *vcpu);
extern void vmx_inject_vhpi(VCPU *vcpu, u8 vec);
-extern void vmx_vcpu_pend_interrupt(VCPU *vcpu, UINT64 vector);
+extern int vmx_vcpu_pend_interrupt(VCPU *vcpu, uint8_t vector);
extern struct virutal_platform_def *vmx_vcpu_get_plat(VCPU *vcpu);
extern void memread_p(VCPU *vcpu, u64 *src, u64 *dest, size_t s);
extern void memread_v(VCPU *vcpu, thash_data_t *vtlb, u64 *src, u64 *dest,
size_t s);
@@ -474,4 +474,7 @@
#endif
}
+
+#define check_work_pending(v) \
+ (event_pending((v)) || ((v)->arch.irq_new_pending))
#endif
diff -r d8c7f144ca54 -r 237b2a4d2499 xen/include/asm-x86/vmx_vlapic.h
--- a/xen/include/asm-x86/vmx_vlapic.h Thu Dec 15 13:49:07 2005
+++ b/xen/include/asm-x86/vmx_vlapic.h Thu Dec 15 13:49:19 2005
@@ -202,6 +202,18 @@
struct domain *domain;
};
+static inline int vlapic_set_irq(struct vlapic *t, uint8_t vec, uint8_t trig)
+{
+ int ret;
+
+ ret = test_and_set_bit(vec, &t->irr[0]);
+ if (trig)
+ test_and_set_bit(vec, &t->tmr[0]);
+
+ /* We may need to wake up target vcpu, besides set pending bit here */
+ return ret;
+}
+
static inline int vlapic_timer_active(struct vlapic *vlapic)
{
return active_ac_timer(&(vlapic->vlapic_timer));
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