# HG changeset patch
# User djm@xxxxxxxxxxxxxxx
# Node ID 6ac2a06e238b514510cdc4f6217d35e6f10a1884
# Parent c35a32f96d2095e92d2e873d9ee842877fa30127
Handle lds on vti domain and fix some bugs on vti domain
Signed-off-by: Anthony Xu <anthony.xu@xxxxxxxxx>
diff -r c35a32f96d20 -r 6ac2a06e238b xen/arch/ia64/vmx/vlsapic.c
--- a/xen/arch/ia64/vmx/vlsapic.c Sat Nov 19 21:41:08 2005
+++ b/xen/arch/ia64/vmx/vlsapic.c Tue Nov 22 18:17:18 2005
@@ -529,7 +529,7 @@
int injected=0;
uint64_t isr;
IA64_PSR vpsr;
-
+ REGS *regs=vcpu_regs(vcpu);
local_irq_save(spsr);
h_pending = highest_pending_irq(vcpu);
if ( h_pending == NULL_VECTOR ) goto chk_irq_exit;
@@ -541,7 +541,7 @@
isr = vpsr.val & IA64_PSR_RI;
if ( !vpsr.ic )
panic("Interrupt when IC=0\n");
- vmx_reflect_interruption(0,isr,0, 12 ); // EXT IRQ
+ vmx_reflect_interruption(0,isr,0, 12, regs ); // EXT IRQ
injected = 1;
}
else if ( mask == IRQ_MASKED_BY_INSVC ) {
@@ -601,13 +601,13 @@
{
IA64_PSR vpsr;
uint64_t isr;
-
+ REGS *regs=vcpu_regs(vcpu);
vpsr.val = vmx_vcpu_get_psr(vcpu);
update_vhpi(vcpu, NULL_VECTOR);
isr = vpsr.val & IA64_PSR_RI;
if ( !vpsr.ic )
panic("Interrupt when IC=0\n");
- vmx_reflect_interruption(0,isr,0, 12 ); // EXT IRQ
+ vmx_reflect_interruption(0,isr,0, 12, regs); // EXT IRQ
}
vhpi_detection(VCPU *vcpu)
diff -r c35a32f96d20 -r 6ac2a06e238b xen/arch/ia64/vmx/vmmu.c
--- a/xen/arch/ia64/vmx/vmmu.c Sat Nov 19 21:41:08 2005
+++ b/xen/arch/ia64/vmx/vmmu.c Tue Nov 22 18:17:18 2005
@@ -438,20 +438,23 @@
thash_data_t *tlb;
ia64_rr vrr;
u64 mfn;
-
+
if ( !(VCPU(vcpu, vpsr) & IA64_PSR_IT) ) { // I-side physical mode
gpip = gip;
}
else {
vmx_vcpu_get_rr(vcpu, gip, &vrr.rrval);
- tlb = vtlb_lookup_ex (vmx_vcpu_get_vtlb(vcpu),
+ tlb = vtlb_lookup_ex (vmx_vcpu_get_vtlb(vcpu),
vrr.rid, gip, ISIDE_TLB );
- if ( tlb == NULL ) panic("No entry found in ITLB\n");
+ if( tlb == NULL )
+ tlb = vtlb_lookup_ex (vmx_vcpu_get_vtlb(vcpu),
+ vrr.rid, gip, DSIDE_TLB );
+ if ( tlb == NULL ) panic("No entry found in ITLB and DTLB\n");
gpip = (tlb->ppn << 12) | ( gip & (PSIZE(tlb->ps)-1) );
}
mfn = __gpfn_to_mfn(vcpu->domain, gpip >>PAGE_SHIFT);
if ( mfn == INVALID_MFN ) return 0;
-
+
mpa = (gpip & (PAGE_SIZE-1)) | (mfn<<PAGE_SHIFT);
*code = *(u64*)__va(mpa);
return 1;
diff -r c35a32f96d20 -r 6ac2a06e238b xen/arch/ia64/vmx/vmx_process.c
--- a/xen/arch/ia64/vmx/vmx_process.c Sat Nov 19 21:41:08 2005
+++ b/xen/arch/ia64/vmx/vmx_process.c Tue Nov 22 18:17:18 2005
@@ -47,6 +47,7 @@
#include <asm/kregs.h>
#include <asm/vmx.h>
#include <asm/vmx_mm_def.h>
+#include <asm/vmx_phy_mode.h>
#include <xen/mm.h>
/* reset all PSR field to 0, except up,mfl,mfh,pk,dt,rt,mc,it */
#define INITIAL_PSR_VALUE_AT_INTERRUPTION 0x0000001808028034
@@ -267,6 +268,12 @@
extern ia64_rr vmx_vcpu_rr(VCPU *vcpu,UINT64 vadr);
+static int vmx_handle_lds(REGS* regs)
+{
+ regs->cr_ipsr |=IA64_PSR_ED;
+ return IA64_FAULT;
+}
+
/* We came here because the H/W VHPT walker failed to find an entry */
void vmx_hpw_miss(u64 vadr , u64 vec, REGS* regs)
{
@@ -294,18 +301,19 @@
return;
}
*/
-
- if((vec==1)&&(!vpsr.it)){
- physical_itlb_miss(v, vadr);
- return;
- }
- if((vec==2)&&(!vpsr.dt)){
- if(v->domain!=dom0&&__gpfn_is_io(v->domain,(vadr<<1)>>(PAGE_SHIFT+1))){
- emulate_io_inst(v,((vadr<<1)>>1),4); // UC
- }else{
- physical_dtlb_miss(v, vadr);
+ if(is_physical_mode(v)&&(!(vadr<<1>>62))){
+ if(vec==1){
+ physical_itlb_miss(v, vadr);
+ return;
}
- return;
+ if(vec==2){
+
if(v->domain!=dom0&&__gpfn_is_io(v->domain,(vadr<<1)>>(PAGE_SHIFT+1))){
+ emulate_io_inst(v,((vadr<<1)>>1),4); // UC
+ }else{
+ physical_dtlb_miss(v, vadr);
+ }
+ return;
+ }
}
vrr = vmx_vcpu_rr(v, vadr);
if(vec == 1) type = ISIDE_TLB;
@@ -336,7 +344,8 @@
} else{
if(misr.sp){
//TODO lds emulation
- panic("Don't support speculation load");
+ //panic("Don't support speculation load");
+ return vmx_handle_lds(regs);
}else{
nested_dtlb(v);
return IA64_FAULT;
@@ -353,8 +362,9 @@
return IA64_FAULT;
}else{
if(misr.sp){
- //TODO lds emulation
- panic("Don't support speculation load");
+ //TODO lds emulation
+ //panic("Don't support speculation load");
+ return vmx_handle_lds(regs);
}else{
nested_dtlb(v);
return IA64_FAULT;
@@ -367,8 +377,9 @@
return IA64_FAULT;
}else{
if(misr.sp){
- //TODO lds emulation
- panic("Don't support speculation load");
+ //TODO lds emulation
+ //panic("Don't support speculation load");
+ return vmx_handle_lds(regs);
}else{
nested_dtlb(v);
return IA64_FAULT;
diff -r c35a32f96d20 -r 6ac2a06e238b xen/arch/ia64/vmx/vmx_virt.c
--- a/xen/arch/ia64/vmx/vmx_virt.c Sat Nov 19 21:41:08 2005
+++ b/xen/arch/ia64/vmx/vmx_virt.c Tue Nov 22 18:17:18 2005
@@ -835,6 +835,7 @@
IA64FAULT vmx_emul_mov_to_dbr(VCPU *vcpu, INST64 inst)
{
+ return IA64_NO_FAULT;
u64 r3,r2;
#ifdef CHECK_FAULT
IA64_PSR vpsr;
@@ -858,6 +859,7 @@
IA64FAULT vmx_emul_mov_to_ibr(VCPU *vcpu, INST64 inst)
{
+ return IA64_NO_FAULT;
u64 r3,r2;
#ifdef CHECK_FAULT
IA64_PSR vpsr;
@@ -1272,8 +1274,7 @@
case 74:return vmx_cr_get(cmcv);
case 80:return vmx_cr_get(lrr0);
case 81:return vmx_cr_get(lrr1);
- default:
- panic("Read reserved cr register");
+ default: return IA64_NO_FAULT;
}
}
diff -r c35a32f96d20 -r 6ac2a06e238b xen/arch/ia64/vmx/vtlb.c
--- a/xen/arch/ia64/vmx/vtlb.c Sat Nov 19 21:41:08 2005
+++ b/xen/arch/ia64/vmx/vtlb.c Tue Nov 22 18:17:18 2005
@@ -391,6 +391,7 @@
#if 1
vrr=vmx_vcpu_rr(current, va);
if (vrr.ps != entry->ps) {
+ machine_tlb_insert(hcb->vcpu, entry);
printk("not preferred ps with va: 0x%lx\n", va);
return;
}
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